/haiku-buildtools/binutils/gas/testsuite/gas/arm/ |
H A D | mul-overlap.l | 2 [^:]*:5: Rd and Rm should be different in mul 3 [^:]*:6: Rd and Rm should be different in mla
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H A D | archv6t2-bad.s | 49 @ ldsttv4 Rd == Rn (warning)
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/haiku-buildtools/binutils/opcodes/ |
H A D | aarch64-tbl.h | 2080 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), 2081 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), 2082 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), 2083 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2084 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), 2085 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2088 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), 2091 CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), 2096 CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), 2099 CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_S [all...] |
H A D | i386-dis-evex.h | 3630 { "vpbroadcastb", { XM, Rd }, 0 }, 3634 { "vpbroadcastw", { XM, Rd }, 0 },
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H A D | i386-dis.c | 281 #define Rd { OP_R, d_mode } macro 11494 { "movL", { Rd, Td }, 0 }, 11499 { "movL", { Td, Rd }, 0 },
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/haiku-buildtools/legacy/binutils/gas/testsuite/gas/arm/ |
H A D | archv6t2-bad.s | 49 @ ldsttv4 Rd == Rn (warning)
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/haiku-buildtools/binutils/gas/config/ |
H A D | tc-arm.c | 6244 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 6277 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 6368 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 6376 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 7190 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been 8359 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 8376 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 8601 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 8652 unsigned Rd; 8655 Rd 8651 unsigned Rd; local 8714 unsigned Rd, Rn; local 8765 unsigned Rd, Rn, Rm; local 10493 int Rd, Rn; local 10515 int Rd, Rs, Rn; local 10733 unsigned Rd; local 10774 int Rd, Rs, Rn; local 10862 int Rd, Rs, Rn; local 10958 unsigned Rd; local 10974 int Rd, Rn; local 11004 unsigned Rd, Rn; local 11194 unsigned Rd; local 11281 unsigned Rd, Rn, Rm; local 11795 unsigned Rd, Rn, Rm, Ra; local 12135 unsigned Rd; local 12248 unsigned Rd; local 12344 unsigned Rd, Rn, Rm; local 12504 unsigned Rd, Rn; local 12538 unsigned Rd, Rn, Rm; local 12623 unsigned Rd, Rm; local 12639 unsigned Rd, Rm; local 12668 unsigned Rd, Rm; local 12683 unsigned Rd, Rs; local 12898 unsigned Rd, Rn, Rm; local 12916 unsigned Rd, Rn, Rm; local 12960 unsigned Rd, Rn; local 13004 unsigned Rd, Rn; local 13054 unsigned Rd, Rn, Rm; local 13073 unsigned Rd, Rm; local 13179 unsigned Rd, Rn; local 17495 unsigned int Rd = inst.operands[0].reg; local [all...] |
/haiku-buildtools/legacy/binutils/gas/config/ |
H A D | tc-arm.c | 4625 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 4642 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 4856 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 4875 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 4885 Result unpredicatable if Rd or Rn is R15. */ 5139 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 5224 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 5226 Error if Rd, Rn or Rm are R15. */ 5388 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 5412 SMLAxy{cond} Rd,R 6166 int Rd, Rn; local 6182 int Rd, Rs, Rn; local 6381 int Rd, Rs, Rn; local 6464 int Rd, Rs, Rn; local 7670 int Rd, Rs; local [all...] |
/haiku-buildtools/legacy/binutils/opcodes/ |
H A D | i386-dis.c | 227 #define Rd OP_Rd, d_mode macro 851 { "movL", Rd, Td, XX }, 853 { "movL", Td, Rd, XX },
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