Searched refs:OPCODE (Results 1 - 25 of 29) sorted by relevance

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/haiku-buildtools/binutils/opcodes/
H A Dspu-opc.c36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
H A Davr-dis.c39 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
40 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
H A Daarch64-tbl.h2045 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
2046 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL }
2047 #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
2048 { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, NULL }
2049 #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
2050 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, NULL }
2051 #define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
2052 { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, NULL }
2053 #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
2054 { NAME, OPCODE, MAS
[all...]
/haiku-buildtools/gcc/gcc/testsuite/g++.dg/debug/dwarf2/
H A Dpr54508.C6 // { dg-final { scan-assembler "\"OPCODE\\\\0\"\[ \t\]+\[#;/!|@\]+ +DW_AT_name" } }
27 OPCODE = 251 enumerator in enum:c::__anon858
63 send(src, c::OPCODE, c::testc (), cookie);
64 send(src, c::OPCODE, s::tests (), cookie);
65 send(src, c::OPCODE, u::testu (), cookie);
66 send(src, c::OPCODE, n::ntest (), cookie);
/haiku-buildtools/legacy/binutils/
H A Dsetup.com7 $ define opcode [-.INCLUDE.OPCODE]
/haiku-buildtools/legacy/gcc/gcc/config/mips/
H A Dmips16.S58 #define SFOP(NAME, OPCODE) \
64 OPCODE $f0,$f0,$f2; \
84 #define SFOP2(NAME, OPCODE) \
89 OPCODE $f0,$f0; \
110 #define SFCMP(NAME, OPCODE, TRUE, FALSE) \
114 OPCODE $f0,$f2; \
124 #define SFREVCMP(NAME, OPCODE, TRUE, FALSE) \
128 OPCODE $f2,$f0; \
234 #define DFOP(NAME, OPCODE) \
240 OPCODE
[all...]
/haiku-buildtools/gcc/libgcc/config/mips/
H A Dmips16.S102 /* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */
103 #define DELAYt(T, OPCODE, OP2) \
106 OPCODE, OP2; \
111 #define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2)
113 /* Use "OPCODE. OP2" and jump to T. */
114 #define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
227 performs FPU operation OPCODE on them, and returns the single-
230 #define OPSF3(NAME, OPCODE) \
[all...]
/haiku-buildtools/binutils/include/opcode/
H A Dspu.h72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
H A Dh8300.h617 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
618 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
619 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
626 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IG
[all...]
/haiku-buildtools/legacy/binutils/include/opcode/
H A Dh8300.h619 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
626 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
627 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
628 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IG
[all...]
/haiku-buildtools/binutils/gas/config/
H A Dtc-rl78.c1035 #define OPCODE(type,size) ((type) * 16 + (size))
1095 switch (OPCODE (rl78_opcode_type (fragP->fr_opcode), fragP->fr_subtype))
1098 case OPCODE (OT_bt, 3): /* BT A,$ - no change. */
1104 case OPCODE (OT_bt, 6): /* BT A,$ - long version. */
1116 case OPCODE (OT_bt_sfr, 4): /* BT PSW,$ - no change. */
1122 case OPCODE (OT_bt_sfr, 7): /* BT PSW,$ - long version. */
1134 case OPCODE (OT_bt_es, 4): /* BT ES:[HL],$ - no change. */
1140 case OPCODE (OT_bt_es, 7): /* BT PSW,$ - long version. */
1152 case OPCODE (OT_bc, 2): /* BC $ - no change. */
1158 case OPCODE (OT_b
1034 #define OPCODE macro
[all...]
H A Dtc-rx.c1748 #define OPCODE(type,size) ((type) * 16 + (size))
1846 switch (OPCODE (rx_opcode_type (fragP->fr_opcode), fragP->fr_subtype))
1848 case OPCODE (OT_bra, 1): /* BRA.S - no change. */
1851 case OPCODE (OT_bra, 2): /* BRA.B - 8 bit. */
1857 case OPCODE (OT_bra, 3): /* BRA.W - 16 bit. */
1869 case OPCODE (OT_bra, 4): /* BRA.A - 24 bit. */
1884 case OPCODE (OT_beq, 1): /* BEQ.S - no change. */
1887 case OPCODE (OT_beq, 2): /* BEQ.B - 8 bit. */
1893 case OPCODE (OT_beq, 3): /* BEQ.W - 16 bit. */
1905 case OPCODE (OT_be
1747 #define OPCODE macro
2159 #undef OPCODE macro
[all...]
H A Dtc-spu.c28 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
29 { MACFORMAT, (OPCODE ## u) << (32-11), MNEMONIC, ASMFORMAT },
30 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
31 { MACFORMAT, ((OPCODE) << (32-11)) | ((FB) << (32-18)), MNEMONIC, ASMFORMAT },
H A Dtc-riscv.c219 /* Handle of the OPCODE hash table. */
274 #define OPCODE_MATCHES(OPCODE, OP) \
275 (((OPCODE) & MASK_##OP) == MATCH_##OP)
H A Dtc-avr.c48 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
49 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
/haiku-buildtools/legacy/binutils/opcodes/
H A Davr-dis.c37 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
38 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
H A Darc-dis.c62 #define OPCODE(word) (BITS ((word), 27, 31)) macro
562 state->_opcode = OPCODE (state->words[0]);
/haiku-buildtools/gcc/gcc/jit/docs/examples/tut04-toyvm/
H A Dtoyvm.c191 #define LINE_MATCHES(OPCODE) (0 == strncmp ((OPCODE), line, strlen (OPCODE)))
H A Dtoyvm.cc219 #define LINE_MATCHES(OPCODE) (0 == strncmp ((OPCODE), line, strlen (OPCODE)))
/haiku-buildtools/legacy/gcc/gcc/java/
H A Djcf-dump.c938 #define JAVAOP(OPNAME, OPCODE, OPKIND, OPERAND_TYPE, OPERAND_VALUE) \
939 case OPCODE: \
H A Dexpr.c2047 #define JAVAOP(OPNAME, OPCODE, OPKIND, OPERAND_TYPE, OPERAND_VALUE) \
2048 case OPCODE: \
2271 #define JAVAOP(OPNAME, OPCODE, OPKIND, OPERAND_TYPE, OPERAND_VALUE) \
2272 case OPCODE: \
/haiku-buildtools/gcc/gcc/java/
H A Djcf-dump.c1511 #define JAVAOP(OPNAME, OPCODE, OPKIND, OPERAND_TYPE, OPERAND_VALUE) \
1512 case OPCODE: \
H A Dexpr.c2424 OPCODE is the specific opcode.
3034 #define JAVAOP(OPNAME, OPCODE, OPKIND, OPERAND_TYPE, OPERAND_VALUE) \
3035 case OPCODE: \
3304 #define JAVAOP(OPNAME, OPCODE, OPKIND, OPERAND_TYPE, OPERAND_VALUE) \
3305 case OPCODE: \
/haiku-buildtools/gcc/gcc/config/mips/
H A Dmips.h2648 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2650 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2651 "%*" OPCODE "%?\t" OPERANDS "%/"
/haiku-buildtools/legacy/binutils/gas/config/
H A Dtc-avr.c39 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \

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