Searched refs:FXM (Results 1 - 2 of 2) sorted by relevance

/haiku-buildtools/legacy/binutils/opcodes/
H A Dppc-opc.c296 /* The FXM field in an XFX instruction. */
297 #define FXM FRS + 1
302 #define FXM4 FXM + 1
1001 /* FXM mask in mfcr and mtcrf instructions. */
1027 /* If only one bit of the FXM field is set, we can use the new form
1739 /* A mask for the FXM version of an XFX form instruction. */
1742 /* An XFX form instruction with the FXM field filled in. */
3328 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3486 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3488 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, R
295 #define FXM macro
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/haiku-buildtools/binutils/opcodes/
H A Dppc-opc.c420 /* The FXM field in an XFX instruction. */
421 #define FXM FRSp + 1
425 #define FXM4 FXM + 1
1427 /* FXM mask in mfcr and mtcrf instructions. */
1446 /* If only one bit of the FXM field is set, we can use the new form
2965 /* A mask for the FXM version of an XFX form instruction. */
2968 /* An XFX form instruction with the FXM field filled in. */
4854 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
5044 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
5045 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, R
419 #define FXM macro
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