Searched refs:FLD_Rm (Results 1 - 5 of 5) sorted by relevance

/haiku-buildtools/binutils/opcodes/
H A Daarch64-opc-2.c30 {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
38 {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register"},
44 {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"},
50 {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
53 {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
58 {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
133 {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
134 {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
135 {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
136 {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "a
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H A Daarch64-opc.h59 FLD_Rm, enumerator in enum:aarch64_field_kind
H A Daarch64-asm.c590 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
693 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
695 insert_field (FLD_Rm, code, 0x1f, 0);
794 insert_field (FLD_Rm, code, info->reg.regno, 0);
815 insert_field (FLD_Rm, code, info->reg.regno, 0);
H A Daarch64-dis.c935 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1053 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1217 info->reg.regno = extract_field (FLD_Rm, code, 0);
1250 info->reg.regno = extract_field (FLD_Rm, code, 0);
H A Daarch64-tbl.h4164 Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
4175 Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \
4185 Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \
4191 Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
4194 Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
4203 Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \
4358 F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
4360 F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
4362 F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
4364 F(FLD_Rn,FLD_Rm), "a
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