Searched refs:vector (Results 1 - 25 of 191) sorted by relevance

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/fuchsia/zircon/third_party/ulib/jemalloc/test/include/test/
H A DSFMT-params11213.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(3,21,21,21,7,0,1,2,11,4,5,6,15,8,9,10)
64 (vector unsigned char)(3,4,5,6,7,29,29,29,11,12,13,14,15,0,1,2)
66 (vector unsigned char)(5,6,7,0,9,10,11,4,13,14,15,8,19,19,19,12)
68 (vector unsigned char)(13,14,15,0,1,2,3,4,19,19,19,8,9,10,11,12)
H A DSFMT-params1279.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(3,21,21,21,7,0,1,2,11,4,5,6,15,8,9,10)
64 (vector unsigned char)(3,4,5,6,7,29,29,29,11,12,13,14,15,0,1,2)
66 (vector unsigned char)(7,0,1,2,11,4,5,6,15,8,9,10,17,12,13,14)
68 (vector unsigned char)(15,0,1,2,3,4,5,6,17,8,9,10,11,12,13,14)
H A DSFMT-params132049.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(1,2,3,23,5,6,7,0,9,10,11,4,13,14,15,8)
64 (vector unsigned char)(1,2,3,4,5,6,7,31,9,10,11,12,13,14,15,0)
66 (vector unsigned char)(7,0,1,2,11,4,5,6,15,8,9,10,17,12,13,14)
68 (vector unsigned char)(15,0,1,2,3,4,5,6,17,8,9,10,11,12,13,14)
H A DSFMT-params216091.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(3,21,21,21,7,0,1,2,11,4,5,6,15,8,9,10)
64 (vector unsigned char)(3,4,5,6,7,29,29,29,11,12,13,14,15,0,1,2)
66 (vector unsigned char)(7,0,1,2,11,4,5,6,15,8,9,10,17,12,13,14)
68 (vector unsigned char)(15,0,1,2,3,4,5,6,17,8,9,10,11,12,13,14)
H A DSFMT-params44497.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(3,21,21,21,7,0,1,2,11,4,5,6,15,8,9,10)
64 (vector unsigned char)(3,4,5,6,7,29,29,29,11,12,13,14,15,0,1,2)
66 (vector unsigned char)(5,6,7,0,9,10,11,4,13,14,15,8,19,19,19,12)
68 (vector unsigned char)(13,14,15,0,1,2,3,4,19,19,19,8,9,10,11,12)
H A DSFMT-params4253.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(1,2,3,23,5,6,7,0,9,10,11,4,13,14,15,8)
64 (vector unsigned char)(1,2,3,4,5,6,7,31,9,10,11,12,13,14,15,0)
66 (vector unsigned char)(7,0,1,2,11,4,5,6,15,8,9,10,17,12,13,14)
68 (vector unsigned char)(15,0,1,2,3,4,5,6,17,8,9,10,11,12,13,14)
H A DSFMT-params19937.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(1,2,3,23,5,6,7,0,9,10,11,4,13,14,15,8)
64 (vector unsigned char)(1,2,3,4,5,6,7,31,9,10,11,12,13,14,15,0)
66 (vector unsigned char)(7,0,1,2,11,4,5,6,15,8,9,10,17,12,13,14)
68 (vector unsigned char)(15,0,1,2,3,4,5,6,17,8,9,10,11,12,13,14)
H A DSFMT-params86243.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(25,25,25,25,3,25,25,25,7,0,1,2,11,4,5,6)
64 (vector unsigned char)(7,25,25,25,25,25,25,25,15,0,1,2,3,4,5,6)
66 (vector unsigned char)(7,0,1,2,11,4,5,6,15,8,9,10,17,12,13,14)
68 (vector unsigned char)(15,0,1,2,3,4,5,6,17,8,9,10,11,12,13,14)
H A DSFMT-params2281.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(1,2,3,23,5,6,7,0,9,10,11,4,13,14,15,8)
64 (vector unsigned char)(1,2,3,4,5,6,7,31,9,10,11,12,13,14,15,0)
66 (vector unsigned char)(7,0,1,2,11,4,5,6,15,8,9,10,17,12,13,14)
68 (vector unsigned char)(15,0,1,2,3,4,5,6,17,8,9,10,11,12,13,14)
H A DSFMT-params607.h56 #define ALTI_SL1 (vector unsigned int)(SL1, SL1, SL1, SL1)
57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1)
58 #define ALTI_MSK (vector unsigned int)(MSK1, MSK2, MSK3, MSK4)
60 (vector unsigned int)(MSK2, MSK1, MSK4, MSK3)
62 (vector unsigned char)(3,21,21,21,7,0,1,2,11,4,5,6,15,8,9,10)
64 (vector unsigned char)(3,4,5,6,7,29,29,29,11,12,13,14,15,0,1,2)
66 (vector unsigned char)(5,6,7,0,9,10,11,4,13,14,15,8,19,19,19,12)
68 (vector unsigned char)(13,14,15,0,1,2,3,4,19,19,19,8,9,10,11,12)
H A DSFMT-alti.h64 vector unsigned int vec_recursion(vector unsigned int a,
65 vector unsigned int b,
66 vector unsigned int c,
67 vector unsigned int d) {
69 const vector unsigned int sl1 = ALTI_SL1;
70 const vector unsigned int sr1 = ALTI_SR1;
72 const vector unsigned int mask = ALTI_MSK64;
73 const vector unsigned char perm_sl = ALTI_SL2_PERM64;
74 const vector unsigne
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/fuchsia/zircon/system/host/fidl/include/fidl/
H A Dsource_manager.h9 #include <vector>
22 const std::vector<std::unique_ptr<SourceFile>>& sources() const { return sources_; }
25 std::vector<std::unique_ptr<SourceFile>> sources_;
H A Derror_reporter.h9 #include <vector>
23 const std::vector<std::string>& errors() const { return errors_; };
26 std::vector<std::string> errors_;
/fuchsia/zircon/kernel/dev/interrupt/arm_gic/common/include/dev/interrupt/
H A Darm_gic_common.h36 static inline zx_status_t gic_register_sgi_handler(unsigned int vector, int_handler handler) { argument
37 DEBUG_ASSERT(vector < GIC_BASE_PPI);
38 return register_int_handler(vector, handler, nullptr);
/fuchsia/zircon/kernel/lib/hypervisor/include/hypervisor/
H A Dinterrupt_tracker.h34 bool TryPop(uint32_t vector) { argument
36 bool has_vector = bitmap_.GetOne(reverse(vector));
38 bitmap_.ClearOne(vector);
44 zx_status_t Pop(uint32_t* vector) { argument
53 *vector = reverse(static_cast<uint32_t>(value));
58 zx_status_t Track(uint32_t vector) { argument
59 if (vector >= N) {
63 bitmap_.SetOne(reverse(vector));
68 zx_status_t Interrupt(uint32_t vector, bool* signaled) { argument
69 zx_status_t status = Track(vector);
104 reverse(uint32_t vector) argument
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/fuchsia/zircon/system/ulib/zx/
H A Dinterrupt.cpp11 zx_status_t interrupt::create(const resource& resource, uint32_t vector, argument
16 resource.get(), vector, options, result->reset_and_get_address());
/fuchsia/zircon/kernel/dev/interrupt/include/dev/
H A Dinterrupt.h29 zx_status_t mask_interrupt(unsigned int vector);
30 zx_status_t unmask_interrupt(unsigned int vector);
39 // Configure the specified interrupt vector. If it is invoked, it muust be
41 zx_status_t configure_interrupt(unsigned int vector,
45 zx_status_t get_interrupt_config(unsigned int vector,
51 zx_status_t register_int_handler(unsigned int vector, int_handler handler, void* arg);
54 // This api will need to evolve if valid vector ranges later are not contiguous
58 bool is_valid_interrupt(unsigned int vector, uint32_t flags);
60 unsigned int remap_interrupt(unsigned int vector);
/fuchsia/zircon/kernel/dev/pdev/include/pdev/
H A Dinterrupt.h20 struct int_handler_struct* pdev_get_int_handler(unsigned int vector);
24 zx_status_t (*mask)(unsigned int vector);
25 zx_status_t (*unmask)(unsigned int vector);
26 zx_status_t (*configure)(unsigned int vector,
29 zx_status_t (*get_config)(unsigned int vector,
32 bool (*is_valid)(unsigned int vector, uint32_t flags);
35 unsigned int (*remap)(unsigned int vector);
/fuchsia/zircon/kernel/dev/interrupt/arm_gic/v2/
H A Darm_gicv2.cpp54 static zx_status_t gic_configure_interrupt(unsigned int vector,
61 static bool gic_is_valid_interrupt(unsigned int vector, uint32_t flags) { argument
62 return (vector < max_irqs);
75 static void gic_set_enable(uint vector, bool enable) { argument
76 int reg = vector / 32;
77 uint32_t mask = (uint32_t)(1ULL << (vector % 32));
192 static zx_status_t gic_mask_interrupt(unsigned int vector) { argument
193 if (vector >= max_irqs) {
197 gic_set_enable(vector, false);
202 static zx_status_t gic_unmask_interrupt(unsigned int vector) { argument
212 gic_configure_interrupt(unsigned int vector, enum interrupt_trigger_mode tm, enum interrupt_polarity pol) argument
240 gic_get_interrupt_config(unsigned int vector, enum interrupt_trigger_mode* tm, enum interrupt_polarity* pol) argument
257 gic_remap_interrupt(unsigned int vector) argument
264 unsigned int vector = iar & 0x3ff; local
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/fuchsia/zircon/kernel/dev/pdev/interrupt/
H A Dinterrupt.c18 struct int_handler_struct* pdev_get_int_handler(unsigned int vector) argument
20 DEBUG_ASSERT(vector < ARM_MAX_INT);
21 return &int_handler_table[vector];
24 zx_status_t register_int_handler(unsigned int vector, int_handler handler, void* arg) argument
26 if (!is_valid_interrupt(vector, 0)) {
35 h = pdev_get_int_handler(vector);
47 static zx_status_t default_mask(unsigned int vector) { argument
51 static zx_status_t default_unmask(unsigned int vector) { argument
55 static zx_status_t default_configure(unsigned int vector, argument
61 static zx_status_t default_get_config(unsigned int vector, argument
67 default_is_valid(unsigned int vector, uint32_t flags) argument
70 default_remap(unsigned int vector) argument
145 mask_interrupt(unsigned int vector) argument
149 unmask_interrupt(unsigned int vector) argument
153 configure_interrupt(unsigned int vector, enum interrupt_trigger_mode tm, enum interrupt_polarity pol) argument
158 get_interrupt_config(unsigned int vector, enum interrupt_trigger_mode* tm, enum interrupt_polarity* pol) argument
171 is_valid_interrupt(unsigned int vector, uint32_t flags) argument
175 remap_interrupt(unsigned int vector) argument
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/fuchsia/zircon/system/host/abigen/parser/
H A Dparser.cpp6 #include <vector>
11 using std::vector;
13 std::vector<string> tokenize_string(const string& str) {
14 std::vector<string> tokens;
34 std::vector<string>& operator+=(std::vector<string>& v1, const std::vector<string>& v2) {
/fuchsia/zircon/system/utest/fbl/
H A Dvector_tests.cpp10 #include <fbl/vector.h>
18 // which should be tested within a vector (raw types,
137 // catch bugs where the vector might call move assignment
156 // Create the vector, verify its contents
158 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
160 vector.reserve(size, &ac);
164 vector.push_back(gen.NextItem(), &ac);
170 ItemType* data = vector.get();
174 ASSERT_EQ(ItemTraits::GetValue(vector[i]), base);
179 // Release the vector'
214 fbl::Vector<ItemType, CountedAllocatorTraits> vector; local
252 fbl::Vector<ItemType, CountedAllocatorTraits> vector; local
290 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
321 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
353 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
410 fbl::Vector<ItemType, FailingAllocatorTraits> vector; local
430 fbl::Vector<ItemType, PartiallyFailingAllocatorTraits<ItemType, size>> vector; local
594 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
635 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
703 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
717 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
732 fbl::Vector<ItemType, TestAllocatorTraits> vector; local
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/fuchsia/zircon/system/host/abigen/
H A Dtypes.h10 #include <vector>
33 std::vector<std::string> multipliers;
37 bool assign_kind(const std::vector<std::string>& attrs);
44 std::vector<std::string> attributes;
62 std::vector<TypeSpec> ret_spec;
63 std::vector<TypeSpec> arg_spec;
64 std::vector<std::string> attributes;
86 bool has_attribute(const char* attr, const std::vector<std::string>& attrs);
87 void dump_attributes(const std::vector<std::string>& attrs);
/fuchsia/zircon/kernel/dev/interrupt/arm_gic/v3/
H A Darm_gicv3.cpp63 static bool gic_is_valid_interrupt(unsigned int vector, uint32_t flags) { argument
64 return (vector < gic_max_int);
88 static void gic_set_enable(uint vector, bool enable) { argument
89 int reg = vector / 32;
90 uint32_t mask = (uint32_t)(1ULL << (vector % 32));
92 if (vector < 32) {
251 static zx_status_t gic_mask_interrupt(unsigned int vector) { argument
252 LTRACEF("vector %u\n", vector);
254 if (vector >
263 gic_unmask_interrupt(unsigned int vector) argument
275 gic_configure_interrupt(unsigned int vector, enum interrupt_trigger_mode tm, enum interrupt_polarity pol) argument
302 gic_get_interrupt_config(unsigned int vector, enum interrupt_trigger_mode* tm, enum interrupt_polarity* pol) argument
321 gic_remap_interrupt(unsigned int vector) argument
330 unsigned vector = iar & 0x3ff; local
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/fuchsia/zircon/kernel/object/include/object/
H A Dinterrupt_event_dispatcher.h18 uint32_t vector,
30 explicit InterruptEventDispatcher(uint32_t vector) argument
31 : vector_(vector) {}

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