Searched refs:regval (Results 1 - 6 of 6) sorted by relevance
| /fuchsia/zircon/system/dev/gpio/aml-gxl-gpio/ |
| H A D | aml-gxl-gpio.c | 139 uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->oen_offset); local
162 regval |= (1 << pin_index);
163 WRITE32_GPIO_REG(block->mmio_index, block->oen_offset, regval);
183 uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->output_offset); local
187 regval |= (1 << (pin_index + block->output_write_shift));
189 regval &= ~(1 << (pin_index + block->output_write_shift));
191 WRITE32_GPIO_REG(block->mmio_index, block->output_offset, regval);
193 regval = READ32_GPIO_REG(block->mmio_index, block->oen_offset);
194 regval &= ~(1 << pin_index);
195 WRITE32_GPIO_REG(block->mmio_index, block->oen_offset, regval);
225 uint32_t regval = READ32_GPIO_REG(gpio_block->mmio_index, reg_index); local
255 const uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->input_offset); local
287 uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->output_offset); local
360 uint32_t regval = READ32_GPIO_INTERRUPT_REG(pin_select_offset); local
[all...] |
| /fuchsia/zircon/system/dev/gpio/aml-axg-gpio/ |
| H A D | aml-axg-gpio.c | 119 uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->oen_offset); local
137 regval |= pinmask;
138 WRITE32_GPIO_REG(block->mmio_index, block->oen_offset, regval);
162 uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->output_offset); local
164 regval |= pinmask;
166 regval &= ~pinmask;
168 WRITE32_GPIO_REG(block->mmio_index, block->output_offset, regval);
170 regval = READ32_GPIO_REG(block->mmio_index, block->oen_offset);
171 regval &= ~pinmask;
172 WRITE32_GPIO_REG(block->mmio_index, block->oen_offset, regval);
211 uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->mux_offset); local
236 const uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->input_offset); local
264 uint32_t regval = READ32_GPIO_REG(block->mmio_index, block->output_offset); local
335 uint32_t regval = READ32_GPIO_INTERRUPT_REG(pin_select_offset); local
[all...] |
| /fuchsia/zircon/system/dev/audio/gauss-pdm-input/ |
| H A D | a113-audio-device.c | 13 #define REGDUMPEEAUDIO(regval) \
14 zxlogf(INFO, #regval " = 0x%08x\n", \
15 a113_ee_audio_read(audio_device, regval));
17 #define REGDUMPPDM(regval) \
18 zxlogf(INFO, #regval " = 0x%08x\n", \
19 a113_ee_audio_read(audio_device, regval));
|
| /fuchsia/zircon/system/dev/pci/amlogic-pcie/ |
| H A D | aml-pcie.cpp | 39 uint32_t regval; local
43 regval = 0;
46 regval = 1;
49 regval = 2;
52 regval = 3;
55 regval = 4;
58 regval = 5;
61 regval = 1;
69 val |= (regval << shift);
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| /fuchsia/zircon/system/dev/i2c/dw-i2c/ |
| H A D | dw-i2c.c | 305 uint32_t regval; local
332 regval = 0;
333 regval = I2C_DW_SET_MASK(regval, DW_I2C_CON_SLAVE_DIS_START,
338 regval = I2C_DW_SET_MASK(regval, DW_I2C_CON_RESTART_EN_START,
343 regval = I2C_DW_SET_MASK(regval, DW_I2C_CON_10BITADDRSLAVE_START,
346 regval = I2C_DW_SET_MASK(regval, DW_I2C_CON_10BITADDRMASTER_STAR
[all...] |
| /fuchsia/zircon/system/dev/display/vim-display/ |
| H A D | hdmitx.cpp | 783 uint32_t regval = 0; local
853 regval = (READ32_REG(VPU, VPU_HDMI_SETTING) & 0xf00) >> 8;
860 SET_BIT32(VPU, VPU_HDMI_SETTING, regval, 4, 8); // why???
864 regval = hdmitx_readreg(display, HDMITX_DWC_FC_INVIDCONF);
865 regval &= ~(1 << 3); // clear hdmi mode select
866 hdmitx_writereg(display,HDMITX_DWC_FC_INVIDCONF, regval);
868 regval = hdmitx_readreg(display, HDMITX_DWC_FC_INVIDCONF);
869 regval |= (1 << 3); // clear hdmi mode select
870 hdmitx_writereg(display,HDMITX_DWC_FC_INVIDCONF, regval);
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