Searched refs:REG_0 (Results 1 - 3 of 3) sorted by relevance

/fuchsia/zircon/system/dev/gpio/aml-gxl-gpio/
H A Ds905-blocks.h128 #define REG_0 S905_PERIPHS_PIN_MUX_0 macro
243 { .regs = { REG_0, REG_0, REG_5, 0, REG_2, REG_7 }, .bits = { 7, 12, 12, 0, 29, 26 }, },
244 { .regs = { REG_0, REG_0, REG_5, 0, REG_2, REG_7 }, .bits = { 6, 11, 11, 0, 28, 27 }, },
245 { .regs = { 0, REG_0, REG_5, 0, REG_2, REG_7 }, .bits = { 0, 10, 10, 0, 27, 24 }, },
246 { .regs = { 0, REG_0, REG_5, REG_5, REG_2, REG_7 }, .bits = { 0, 9, 9, 8, 26, 25 }, },
322 #undef REG_0 macro
H A Ds905x-blocks.h115 #define REG_0 S905X_PERIPHS_PIN_MUX_0 macro
289 #undef REG_0 macro
H A Ds912-blocks.h115 #define REG_0 S912_PERIPHS_PIN_MUX_0 macro
290 #undef REG_0 macro

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