Searched refs:setRegClass (Results 1 - 25 of 37) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp295 MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::IDRegClass);
432 MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass);
452 MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass);
464 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
465 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
477 MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
484 MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::IDRegClass);
492 MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
516 MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
521 MIRBuilder.getMRI()->setRegClass(Cal
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H A DSPIRVPreLegalizer.cpp90 MRI.setRegClass(Reg, RC);
206 MRI.setRegClass(Reg, &SPIRV::IDRegClass);
228 MRI.setRegClass(NewReg, RC);
230 MRI.setRegClass(NewReg, &SPIRV::IDRegClass);
231 MRI.setRegClass(Reg, &SPIRV::IDRegClass);
365 MRI.setRegClass(IdReg, DstClass);
416 MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
H A DSPIRVGlobalRegistry.cpp65 MRI.setRegClass(Res, &SPIRV::TYPERegClass);
71 MRI.setRegClass(Res, &SPIRV::TYPERegClass);
154 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
214 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
257 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
289 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
361 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
430 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
1170 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
H A DSPIRVCallLowering.cpp351 MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
371 MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
463 MRI->setRegClass(Reg, &SPIRV::IDRegClass);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp54 /// setRegClass - Set the register class of the specified virtual register.
57 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { function in class:MachineRegisterInfo
79 MRI.setRegClass(Reg, NewRC);
141 setRegClass(Reg, NewRC);
H A DTailDuplicator.cpp425 MRI->setRegClass(VI->second.Reg, ConstrRC);
H A DRegisterBankInfo.cpp148 MRI.setRegClass(Reg, &RC);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp186 MRI.setRegClass(SrcReg, DstRC);
H A DInlineAsmLowering.cpp364 Flag.setRegClass(RC->getID());
515 Flag.setRegClass(RC->getID());
/freebsd-current/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h375 // setRegClass() uses 0 to mean no register class, and otherwise stores
397 /// setRegClass - Augment an existing flag with the required register class
400 void setRegClass(unsigned RC) { function in class:llvm::final::Flag
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp411 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
1314 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1318 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1331 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1340 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
2427 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2429 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp247 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
299 MRI.setRegClass(DstReg, DstRC);
823 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0));
H A DSIFoldOperands.cpp2024 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC));
2026 MRI->setRegClass(DefReg, RC);
2032 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg)));
H A DAMDGPURegisterBankInfo.cpp941 MRI.setRegClass(CondReg, WaveRC);
2570 MRI.setRegClass(DstReg, &AMDGPU::SGPR_64RegClass);
2571 MRI.setRegClass(SrcReg0, &AMDGPU::SGPR_64RegClass);
2572 MRI.setRegClass(SrcReg1, &AMDGPU::SGPR_64RegClass);
2585 MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass);
2591 MRI.setRegClass(Op1L, &AMDGPU::VGPR_32RegClass);
2601 MRI.setRegClass(Zero64, &AMDGPU::VReg_64RegClass);
2603 MRI.setRegClass(CarryOut, &AMDGPU::VReg_64RegClass);
H A DSILowerI1Copies.cpp810 MRI->setRegClass(DstReg, ST->getBoolRC());
H A DAMDGPUInstructionSelector.cpp184 MRI->setRegClass(SrcReg, SrcRC);
463 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass);
1042 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
1573 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
2196 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
2925 MRI->setRegClass(CondReg, ConstrainRC);
H A DAMDGPULegalizerInfo.cpp2131 MRI.setRegClass(Dst, &AMDGPU::SReg_64RegClass);
2791 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);
2813 MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass);
2826 MRI.setRegClass(AddrHi, &AMDGPU::SReg_32RegClass);
2839 MRI.setRegClass(AddrDst, &AMDGPU::SReg_64RegClass);
6949 MRI.setRegClass(Def, TRI->getWaveMaskRegClass());
6950 MRI.setRegClass(Use, TRI->getWaveMaskRegClass());
6985 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp299 Flag.setRegClass(SP::IntPairRegClassID);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp254 Flag.setRegClass(CSKY::GPRPairRegClassID);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1332 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1334 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1336 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1334 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass);
1356 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass);
2072 MRI.setRegClass(NewMI.getReg(0), &AArch64::GPR64commonRegClass);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp507 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain));
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h701 /// setRegClass - Set the register class of the specified virtual register.
702 void setRegClass(Register Reg, const TargetRegisterClass *RC);
781 /// undefined on an incomplete register until one of setRegClass(),
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI));
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp698 MRI.setRegClass(Reg, Info.D.RC);

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