Searched refs:ShiftWidth (Results 1 - 8 of 8) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.h49 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
H A DLoongArchISelDAGToDAG.cpp227 bool LoongArchDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, argument
237 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
238 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1);
255 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
259 if (lsb == 0 && Log2_32(ShiftWidth) <= msb + 1) {
268 if (Imm != 0 && Imm % ShiftWidth == 0) {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp172 unsigned ShiftWidth = ShiftLLT.getSizeInBits(); local
173 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
183 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1);
198 if (Imm != 0 && Imm.urem(ShiftWidth) == 0)
203 if (Imm != 0 && Imm.urem(ShiftWidth) == 0) {
214 if (Imm.urem(ShiftWidth) == ShiftWidth - 1) {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h87 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
H A DRISCVISelDAGToDAG.cpp2545 bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, argument
2562 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
2563 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1);
2582 if (Imm != 0 && Imm % ShiftWidth == 0) {
2591 if (Imm != 0 && Imm % ShiftWidth == 0) {
2603 if (Imm % ShiftWidth == ShiftWidth - 1) {
/freebsd-current/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h2538 unsigned ShiftWidth = TypeSize - 1; local
2551 auto LHS = m_AShr(m_Value(OpL), m_SpecificInt(ShiftWidth));
2552 auto RHS = m_LShr(m_Neg(m_Value(OpR)), m_SpecificInt(ShiftWidth));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1316 AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
1326 bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1329 !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8)
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1534 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16)); local
1539 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);

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