Searched refs:Shift1 (Results 1 - 6 of 6) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp732 uint64_t Shift1 = 0, Shift2 = 0; local
734 Shift1 = ShAmt1->getZExtValue();
752 if ((Shift2 - Shift1) != ShiftDiff || (Offset2 - Offset1) != PrevSize)
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp743 bool Shift1 = mi_match( local
747 if (Shift0 && Shift1) {
751 } else if (Shift1) {
/freebsd-current/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp2044 const APInt *Shift1, *Shift2; local
2045 if (match(Op0, m_Shl(m_Value(X), m_APInt(Shift1))) &&
2049 Shift1->uge(*Shift2))
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1795 Register Shift1 = local
1812 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2});
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp7612 SDValue Shift1 = N1.getOperand(0); local
7613 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
7616 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1));
7621 if (Shift0.getOperand(0) != Shift1.getOperand(0))
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp[all...]

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