/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiAluCode.h | 35 SRL = 0x27, enumerator in enum:llvm::LPAC::AluCode 93 case SRL: 112 .Case("srl", SRL)
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H A D | LanaiISelDAGToDAG.cpp | 236 case ISD::SRL: 237 return AluCode::SRL;
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H A D | LanaiMemAluCombiner.cpp | 221 return LPAC::SRL;
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/freebsd-current/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-mips.pl | 103 $SRL="dsrl"; # shift right logical 118 $SRL="srl"; # shift right logical 216 $SRL $h,$e,@Sigma1[0] 220 $SRL $tmp0,$e,@Sigma1[1] 224 $SRL $tmp0,$e,@Sigma1[2] 231 $SRL $h,$a,@Sigma0[0] 236 $SRL $tmp0,$a,@Sigma0[1] 240 $SRL $tmp0,$a,@Sigma0[2] 267 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i) 273 $SRL [all...] |
H A D | sha512-sparcv9.pl | 70 $SRL="srlx"; # shift right logical 96 $SRL="srl"; # shift right logical 234 $SRL $e,@Sigma1[0],$h !! $i 238 $SRL $e,@Sigma1[1],$tmp0 242 $SRL $e,@Sigma1[2],$tmp0 249 $SRL $a,@Sigma0[0],$h 254 $SRL $a,@Sigma0[1],$tmp0 258 $SRL $a,@Sigma0[2],$tmp0
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr;
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H A D | ARMISelLowering.cpp | 195 setOperationAction(ISD::SRL, VT, Custom); 258 setOperationAction(ISD::SRL, VT, Custom); 1002 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, 1171 setOperationAction(ISD::SRL, MVT::i64, Custom); 1179 // assuming that ISD::SRL and SRA of i64 are already marked custom 1594 setTargetDAGCombine(ISD::SRL); 1998 if (Op.getOpcode() != ISD::SRL) 6315 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 6321 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 6363 SDValue Tmp1 = DAG.getNode(ISD::SRL, d [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 313 // normally expanded to the sequence SRA + SRL + ADD + SRA. 350 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. 353 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand. 356 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand. 360 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw 363 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw 375 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand. 379 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split. 383 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, // psrld 386 { ISD::SRL, MV [all...] |
H A D | X86ISelDAGToDAG.cpp | 752 case ISD::SRL: 1151 case ISD::SRL: { 1162 case ISD::SRL: NewOpc = X86ISD::VSRLV; break; 1991 if (Shift.getOpcode() != ISD::SRL || 2006 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); 2130 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || 2192 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); 2223 if (Shift.getOpcode() != ISD::SRL || 2252 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); 2486 case ISD::SRL [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 946 assert((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && 947 "SRL or SRA node is required here!"); 1024 case ISD::SRL: { 1599 if ((Op0Opcode == ISD::SRL || Op0Opcode == ISD::SHL) && Op0.hasOneUse()) { 1737 if (Op0.getOpcode() == ISD::SRL) { 1746 Opc = ISD::SRL; 1777 if (InnerOp.getOpcode() == ISD::SRL && Op0.hasOneUse() && 1897 case ISD::SRL: { 1922 unsigned Opc = ISD::SRL; 1948 isTypeDesirableForOp(ISD::SRL, HalfV [all...] |
H A D | LegalizeIntegerTypes.cpp | 107 case ISD::SRL: 484 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, 539 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 567 return DAG.getNode(ISD::SRL, dl, NVT, 991 ShiftOp = ISD::SRL; 1054 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; 1156 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, 1416 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt); 1418 Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift); 1677 DAG.getNode(ISD::SRL, D [all...] |
H A D | DAGCombiner.cpp | 1682 else if (Opc == ISD::SRL) 1973 case ISD::SRL: return visitSRL(N); 2120 case ISD::SRL: 2548 BinOpcode == ISD::SRL) && Sel.hasOneUse()) { 2675 ShiftOp.getOpcode() != ISD::SRL) 2697 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, 3849 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { 3852 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; 4112 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { 4845 SDValue Srl = DAG.getNode(ISD::SRL, D 14255 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; local [all...] |
H A D | LegalizeVectorOps.cpp | 104 /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA. 361 case ISD::SRL: 1351 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && 1389 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && 1406 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && 1602 // Make sure that the SINT_TO_FP and SRL instructions are available. 1607 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) { 1634 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord);
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/freebsd-current/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
H A D | RISCVInstructions.h | 133 R_TYPE_INST(SRL); 277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 87 setOperationAction(ISD::SRL, MVT::i8, Custom); 90 setOperationAction(ISD::SRL, MVT::i16, Custom); 93 setOperationAction(ISD::SRL, MVT::i32, Custom); 312 case ISD::SRL: { 326 case ISD::SRL: 346 case ISD::SRL: 384 case ISD::SRL: 402 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && 414 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { 486 case ISD::SRL [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCCodeEmitter.cpp | 242 case LPAC::SRL:
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 707 SRL, enumerator in enum:llvm::ISD::NodeType
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/freebsd-current/crypto/openssl/crypto/bn/asm/ |
H A D | mips.pl | 69 $SRL="dsrl"; 84 $SRL="srl"; 930 $SRL $at,$a1,$t1 945 $SRL $DH,$a2,4*$BNSZ # bits 954 $SRL $HH,$a0,4*$BNSZ # bits 955 $SRL $QT,4*$BNSZ # q=0xffffffff 962 $SRL $at,$a1,4*$BNSZ # bits 987 $SRL $HH,$a0,4*$BNSZ # bits 988 $SRL $QT,4*$BNSZ # q=0xffffffff 995 $SRL [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 126 setOperationAction(ISD::SRL, MVT::i32, Custom); 261 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); 307 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); 334 setTargetDAGCombine(ISD::SRL); 1571 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); 1573 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt); 1604 // SRL expansion: 1612 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; 1621 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 1650 case ISD::SRL [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 800 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 940 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 1204 N->getOperand(0).getOpcode() == ISD::SRL) || 1205 (N->getOpcode() == ISD::SRL && 2363 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2364 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2413 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2414 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2460 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2494 Res = DAG.getNode(ISD::SRL, D 2747 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZShortenInst.cpp | 369 TwoOperandOpcode == SystemZ::SRL ||
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 1704 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 1839 if (Op.getOperand(0).getOpcode() != ISD::SRL) 1950 case ISD::SRL: 1962 APInt Mask = ArithOp.getOpcode() == ISD::SRL 3454 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); 3456 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt); 3486 // SRL expansion: 3494 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; 3505 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 77 setOperationAction(ISD::SRL, MVT::i8, Custom); 80 setOperationAction(ISD::SRL, MVT::i16, Custom); 343 case ISD::SRL: 984 case ISD::SRL: 996 if (Opc == ISD::SRL && ShiftAmount) { 1199 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 461 ISD::SRA, ISD::SRL, ISD::ROTL, 569 ISD::SRA, ISD::SRL, 991 N->getOpcode() == ISD::SRL) && 1002 N->use_begin()->getOpcode() == ISD::SRL)) 2168 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); 3492 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, 3496 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, 3505 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, 3537 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); 3545 V = DAG.getNode(ISD::SRL, D [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 642 case ISD::SRL: 715 if (LHSOpcode != ISD::SHL && LHSOpcode != ISD::SRL && LHSOpcode != ISD::SRA) 757 // SRL high bits can be 0 or 1 758 if (LHSOpcode == ISD::SRL && (BitWidth > (NewShiftC + MaskLen))) 761 if (LHSOpcode == ISD::SRL) 2324 // Handle the SRL + ANY_EXTEND case. 2326 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) { 2327 // Extend the incoming operand of the SRL to 64-bit. 2333 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, 2338 // Use the type of SRL nod [all...] |