| /freebsd-current/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | BPF.cpp | 40 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), 64); local
41 CoerceTy = llvm::ArrayType::get(RegTy, 2);
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| H A D | PPC.cpp | 824 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits); local
825 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 489 bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy, argument
496 unsigned RegSize = RegTy.getSizeInBits();
514 if (RegTy.isVector() && MainTy.isVector()) {
515 unsigned RegNumElts = RegTy.getNumElements();
521 RegTy.getScalarSizeInBits() == MainTy.getScalarSizeInBits() &&
524 LLT::fixed_vector(LeftoverNumElts, RegTy.getScalarSizeInBits());
588 LLT RegTy = MRI.getType(Reg); local
589 assert(RegTy.isVector() && "Expected a vector type");
591 LLT EltTy = RegTy.getElementType();
593 unsigned RegNumElts = RegTy
880 getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy) argument
[all...] |
| H A D | RegBankSelect.cpp | 174 LLT RegTy = MRI->getType(MO.getReg()); local
177 if (RegTy.isVector()) {
178 if (ValMapping.NumBreakDowns == RegTy.getNumElements())
183 RegTy.getSizeInBits()) &&
184 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() ==
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| H A D | CallLowering.cpp | 1272 const LLT RegTy = MRI.getType(ValVReg); local
1274 if (isCopyCompatibleType(RegTy, LocTy)) {
1280 auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy);
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| H A D | CombinerHelper.cpp | 764 LLT RegTy = MRI.getType(LoadReg); local
766 unsigned RegSize = RegTy.getSizeInBits();
797 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}}))
877 LLT RegTy = MRI.getType(DstReg); local
880 if (RegTy.isVector())
910 else if (MemBits > NewSizeBits || MemBits == RegTy.getSizeInBits())
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| H A D | LegalizerHelper.cpp | 5571 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); local
5574 extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left,
5576 extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left, MIRBuilder,
5608 insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy,
5748 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); local
5750 extractParts(MI.getOperand(1).getReg(), RegTy, NarrowTy, LeftoverTy, SrcRegs,
5812 if (WideSize > RegTy.getSizeInBits()) {
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 451 LLT RegTy = MRI.getType(Op.getReg()); local
453 if (RegTy.isScalar() &&
454 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64))
457 if (RegTy.isVector() && RegTy.getSizeInBits() != 128)
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| H A D | MipsCallLowering.cpp | 428 LLT RegTy = LLT::scalar(RegSize * 8); local
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I]));
437 MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize));
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| H A D | MipsISelLowering.cpp | 4386 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4387 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4395 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4415 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); local
4427 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4454 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4466 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4470 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4505 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); local
4506 const TargetRegisterClass *RC = getRegClassFor(RegTy);
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 94 const LLT RegTy = getType(Reg); local
96 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
97 RegTy != ConstrainingRegTy)
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 259 bool extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
336 /// RegTy. This assumes all references to the register will use the same type.
344 const DebugLoc &DL, LLT RegTy = LLT());
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1586 const LLT RegTy = MRI.getType(DstReg); local
1587 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
1674 auto OpEntryIt = llvm::find_if(OpTable, [RegTy](const MulDivRemEntry &El) {
1675 return El.SizeInBits == RegTy.getSizeInBits();
1711 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
1738 if (RegTy.getSizeInBits() == 16) {
1742 } else if (RegTy.getSizeInBits() == 32) {
1746 } else if (RegTy.getSizeInBits() == 64) {
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 200 struct RegTy { struct in struct:__anon2428::HexagonOperand
210 struct RegTy Reg;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1810 template <VecListIndexType RegTy, unsigned NumRegs>
1827 assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) &&
1830 assert((RegTy != VecListIdx_PReg || NumRegs <= 2) &&
1833 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs];
1835 FirstRegs[(unsigned)RegTy][0]));
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 6346 LLT RegTy;
6352 RegTy = S32;
6360 RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32;
6414 ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy);
6444 if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) {
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3955 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32; local
3960 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops);
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