Searched refs:RH (Results 1 - 13 of 13) sorted by relevance

/freebsd-current/bin/chmod/tests/
H A Dchmod_test.sh47 atf_check chmod -RH 0700 A
49 atf_check chmod -RH 0600 A/C
/freebsd-current/usr.sbin/chown/tests/
H A Dchown_test.sh48 atf_check chown -RH 84:84 A
50 atf_check chown -RH 126:126 A/C
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp507 SDValue LL, LH, RL, RH, CL, CH; local
511 GetSplitOp(N->getOperand(2), RL, RH);
542 Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH);
551 Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH, EVLHi);
556 SDValue LL, LH, RL, RH; local
559 GetSplitOp(N->getOperand(3), RL, RH);
564 N->getOperand(1), LH, RH, N->getOperand(4));
H A DLegalizeIntegerTypes.cpp3977 SDValue LL, LH, RL, RH; local
3979 GetExpandedInteger(N->getOperand(1), RL, RH);
3981 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
3990 SDValue LL, LH, RL, RH; local
3992 GetExpandedInteger(N->getOperand(1), RL, RH);
3996 LL, LH, RL, RH))
4047 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
4140 SDValue LL, LH, RL, RH; local
4142 GetExpandedInteger(RHS, RL, RH);
4148 LL, LH, RL, RH)) {
[all...]
H A DTargetLowering.cpp7404 SDValue LH, SDValue RL, SDValue RH) const {
7423 // LL, LH, RL, and RH must be either all NULL or all set to a value.
7424 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
7425 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
7485 if (!LH.getNode() && !RH.getNode() &&
7490 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
7491 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
7503 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
[all...]
H A DLegalizeVectorTypes.cpp2274 SDValue LL, LH, RL, RH; local
2283 GetSplitVector(N->getOperand(1), RL, RH);
2285 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
2289 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
2298 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2), MaskHi,
/freebsd-current/bin/cp/tests/
H A Dcp_test.sh130 atf_check cp -RH coo foo/moo
153 atf_check cp -RH roo foo
210 atf_check cp -RH foo foo-mirror
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1734 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
1736 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI);
1789 unsigned B, RegHalf &RH);
1830 // set the information about the found register in RH.
1832 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) {
1899 RH.Reg = Reg;
1900 RH.Sub = Sub;
1901 RH.Low = Low;
1903 if (!HBS::getFinalVRegClass(RH, MR
[all...]
H A DHexagonConstPropagation.cpp1861 bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
2515 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, argument
2517 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg));
2519 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH))
/freebsd-current/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp667 SDValue LH, RH; local
670 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
676 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
678 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h5030 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
5036 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
5045 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
5050 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
/freebsd-current/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLowerMatrixIntrinsics.cpp1514 Value *RH = Builder.CreateExtractElement( local
1517 Value *Splat = Builder.CreateVectorSplat(BlockSize, RH, "splat");
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4121 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); local
4127 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);

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