Searched refs:PtrReg (Results 1 - 11 of 11) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp331 Register PtrReg = Store.getPointerReg(); local
333 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg,
338 B.buildStore(Zero, PtrReg, *LowMMO);
664 Register PtrReg = St->getPointerReg(); local
666 PtrReg, MRI,
668 GPtrAdd *PtrAdd = cast<GPtrAdd>(MRI.getVRegDef(PtrReg));
H A DAArch64InstructionSelector.cpp2924 const Register PtrReg = LdSt.getPointerReg();
2925 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
2929 assert(MRI.getType(PtrReg).isPointer() &&
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp430 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); local
431 lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]);
450 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO);
561 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); local
562 lowerParameterPtr(PtrReg, B, ArgOffset);
564 B.buildAddrSpaceCast(VRegs[i][0], PtrReg);
H A DAMDGPURegisterBankInfo.cpp1089 Register PtrReg = MI.getOperand(1).getReg();
1099 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1103 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1107 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0);
1121 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0);
3425 Register PtrReg = MI.getOperand(0).getReg(); local
3426 unsigned PtrBank = getRegBankID(PtrReg, MRI, AMDGPU::SGPRRegBankID);
3431 unsigned AS = MRI.getType(PtrReg).getAddressSpace();
3622 Register PtrReg) const {
3623 LLT PtrTy = MRI.getType(PtrReg);
[all...]
H A DAMDGPULegalizerInfo.cpp2974 Register PtrReg = MI.getOperand(1).getReg();
2975 LLT PtrTy = MRI.getType(PtrReg);
2980 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg);
3032 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
3040 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
3045 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
3102 Register PtrReg = MI.getOperand(1).getReg();
3106 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) &&
3116 .addUse(PtrReg)
H A DAMDGPUInstructionSelector.cpp4308 Register PtrReg = GEPInfo.SgprParts[0];
4315 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp746 Register PtrReg = Op.getReg();
747 assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer!");
750 auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp765 Register PtrReg = LoadMI->getPointerReg(); local
797 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}}))
805 B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO);
2299 MachineInstr &MI, std::pair<Register, bool> &PtrReg) {
2307 PtrReg.second = false;
2309 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) {
2312 LLT PtrTy = MRI.getType(PtrReg.first);
2317 PtrReg.second = true;
2324 MachineInstr &MI, std::pair<Register, bool> &PtrReg) {
2329 const bool DoCommute = PtrReg
2298 matchCombineAddP2IToPtrAdd( MachineInstr &MI, std::pair<Register, bool> &PtrReg) argument
2323 applyCombineAddP2IToPtrAdd( MachineInstr &MI, std::pair<Register, bool> &PtrReg) argument
[all...]
H A DLegalizerHelper.cpp1334 Register PtrReg = LoadMI.getPointerReg(); local
1341 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1343 MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), TmpReg, PtrReg, MMO);
3300 Register PtrReg = LoadMI.getPointerReg(); local
3330 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO);
3333 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO);
3338 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO);
3400 LLT PtrTy = MRI.getType(PtrReg);
3404 PtrReg, *LargeMMO);
3409 auto SmallPtr = MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCs
3442 Register PtrReg = StoreMI.getPointerReg(); local
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12074 Register PtrReg = RegInfo.createVirtualRegister(RC); local
12136 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
12141 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
12162 .addReg(PtrReg);
12205 .addReg(PtrReg);
13066 Register PtrReg = RegInfo.createVirtualRegister(RC); local
13135 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
13140 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
13172 .addReg(PtrReg);
13196 .addReg(PtrReg);
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5114 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; local
5115 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg,

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