| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 69 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
150 bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
169 buildMI(MBB, MBBI, OpHi)
369 unsigned OpHi = AVR::SBCIRdK; local
382 buildMI(MBB, MBBI, OpHi)
431 unsigned OpHi = AVR::COMRd; local
443 buildMI(MBB, MBBI, OpHi)
503 unsigned OpHi = AVR::CPCRdRr; local
512 auto MIBHI = buildMI(MBB, MBBI, OpHi)
536 unsigned OpHi local
568 unsigned OpHi = AVR::LDIRdK; local
619 unsigned OpHi = AVR::LDSRdK; local
711 unsigned OpHi = AVR::LDRdPtrPi; local
744 unsigned OpHi = AVR::LDRdPtrPd; local
861 unsigned OpHi = IsELPM ? AVR::ELPMRdZ : AVR::LPMRdZ; local
1208 unsigned OpHi = AVR::STPtrPiRr; local
1243 unsigned OpHi = AVR::STPtrPdRr; local
1386 unsigned OpHi = AVR::INRdA; local
1450 unsigned OpHi = AVR::PUSHRr; local
1474 unsigned OpHi = AVR::POPRd; local
1569 unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd local
1770 unsigned OpHi = AVR::LSRRd; local
1980 unsigned OpHi = AVR::ASRRd; local
2507 unsigned OpHi = AVR::INRdA; local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1962 const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1); local
1964 RegisterSubReg SrcRL(OpLo), SrcRH(OpHi);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2397 MachineOperand OpHi = MI.getOperand(2);
2427 if (OpHi.isGlobal())
2428 OpHi.setOffset(OpHi.getOffset() + Adjust + 12);
2431 .add(OpHi));
|
| H A D | SIISelLowering.cpp | 5457 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi, local
5460 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
5483 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, local
5486 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
5515 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, local
5518 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
|
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1634 SDValue OpHi = Op; local
1641 GetSplitVector(Op, OpLo, OpHi);
1643 std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i);
1647 OpsHi[i] = OpHi;
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20017 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
20018 OpHi = DAG.getBitcast(HalfVT, OpHi);
20020 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
20595 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
20599 DAG.getBitcast(MVT::v4i32, OpHi), ShufMask);
24383 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, In, ShufMask);
24384 OpHi = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, HalfVT, OpHi);
24386 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
[all...] |