/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 68 const MachineOperand &MO2); 73 const MachineOperand &MO2); 202 const MachineOperand &MO2) { 203 return MO1.isIdenticalTo(MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical()); 214 const MachineOperand &MO2) { 215 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && 217 return (MO1.isImm() && MO2.isImm()) || 218 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || 219 (MO1.isJTI() && MO2 201 isIdenticalOp(const MachineOperand &MO1, const MachineOperand &MO2) argument 213 isSimilarDispOp(const MachineOperand &MO1, const MachineOperand &MO2) argument [all...] |
H A D | X86RegisterInfo.cpp | 1061 MachineOperand &MO2 = MI->getOperand(2); 1062 ShapeT Shape(&MO1, &MO2, MRI);
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 99 const MCOperand &MO2 = MI->getOperand(2); local 112 printRegName(O, MO2.getReg()); 122 const MCOperand &MO2 = MI->getOperand(2); local 124 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 133 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 140 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 398 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 410 printRegName(O, MO2.getReg()); 418 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 423 printRegImmShift(O, ARM_AM::getSORegShOp(MO2 [all...] |
H A D | ARMMCTargetDesc.cpp | 448 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); local 449 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 452 int32_t OffImm = (int32_t)MO2.getImm(); 466 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); local 468 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) 486 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); local 487 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 490 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 491 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); 505 const MCOperand &MO2 local 525 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); local [all...] |
H A D | ARMMCCodeEmitter.cpp | 921 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); local 923 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1275 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1278 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1279 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1280 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1369 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1384 unsigned Imm = MO2.getImm(); 1532 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1533 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2 [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCCodeEmitter.cpp | 129 const MCOperand &MO2 = MI.getOperand(Op + 1); local 130 if (MO2.isImm()) { 132 return ((unsigned)MO2.getImm() << 4) | Reg; 135 assert(MO2.isExpr() && "Expr operand expected"); 148 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(),
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchExpandPseudoInsts.cpp | 449 // Part2: lu32i.d $t8, %MO2(sym) 453 unsigned MO0, MO1, MO2, MO3; local 460 MO2 = LoongArchII::MO_PCREL64_LO; 469 MO2 = LoongArchII::MO_GOT_PC64_LO; 475 MO2 = LoongArchII::MO_IE_PC64_LO; 503 Part2.addExternalSymbol(SymName, MO2); 508 Part2.addDisp(Symbol, 0, MO2);
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1232 MCOperand &MO2) { 1237 TmpInst.addOperand(MO2); 1594 MCOperand &MO2 = Inst.getOperand(2); local 1596 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { 1601 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); 1615 MCOperand &MO2 = Inst.getOperand(2); local 1616 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); 1231 makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, MCOperand &MO2) argument
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 925 MachineOperand &MO2 = Cond[2]; 926 switch (MO2.getReg()) { 928 MO2.setReg(R600::PRED_SEL_ONE); 931 MO2.setReg(R600::PRED_SEL_ZERO);
|
H A D | SIInstrInfo.cpp | 533 auto MO2 = *MI2.memoperands_begin(); 534 if (MO1->getAddrSpace() != MO2->getAddrSpace()) 538 auto Base2 = MO2->getValue();
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 453 MCOperand &MO2 = MappedInst.getOperand(2); local 454 MCExpr const *Expr = MO2.getExpr();
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 2257 auto MO2 = *MI2.memoperands_begin(); local 2258 if (MO1->getAddrSpace() != MO2->getAddrSpace()) 2262 auto Base2 = MO2->getValue();
|
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineScheduler.cpp | 1172 for (const MachineOperand &MO2 : MI.all_defs()) { 1173 if (MO2.getReg() == Reg && !MO2.isDead()) {
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 733 for (auto MO2 : DefMI->uses()) 734 if (MO2.isCPI()) 735 return (MCP->getConstants())[MO2.getIndex()].Val.ConstVal;
|
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 1577 MachineOperand &MO2 = MI.getOperand(0); local 1580 MIRBuilder.buildSExt(MO2, DstExt); 1581 MO2.setReg(DstExt);
|