/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
H A D | RISCVCustomBehaviour.cpp | 46 const llvm::StringRef RISCVLMULInstrument::DESC_NAME = "RISCV-LMUL"; 49 // Return true if not one of the valid LMUL strings 59 "Cannot get LMUL because invalid Data value"); 60 // These are the LMUL values that are used in RISC-V tablegen 84 // These are the LMUL values that are used in RISC-V tablegen 132 StringRef LMUL; local 135 LMUL = "M1"; 138 LMUL = "M2"; 141 LMUL = "M4"; 144 LMUL 189 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) argument 263 uint8_t LMUL = LI->getLMUL(); local [all...] |
/freebsd-current/contrib/llvm-project/clang/lib/Support/ |
H A D | RISCVVIntrinsicUtils.cpp | 38 assert(NewLog2LMUL <= 3 && NewLog2LMUL >= -3 && "Bad LMUL number!"); 76 : BT(BT), LMUL(LMULType(Log2LMUL)) { 90 // boolean type are encoded the ratio of n (SEW/LMUL) 91 // SEW/LMUL | 1 | 2 | 4 | 8 | 16 | 32 | 64 120 if (IsTuple && (1 << std::max(0, LMUL.Log2LMUL)) * NF > 8) 255 ClangBuiltinStr += utostr(ElementBitwidth) + LMUL.str() + 268 return Twine("v" + TypeStr + Twine(ElementBitwidth) + LMUL.str() + 356 ShortStr += LMUL.str(); 679 Scale = LMUL.getScale(ElementBitwidth); 708 LMUL [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.h | 203 uint16_t LMUL : 3; member in struct:llvm::RISCV::VLSEGPseudo 212 uint16_t LMUL : 3; member in struct:llvm::RISCV::VLXSEGPseudo 222 uint16_t LMUL : 3; member in struct:llvm::RISCV::VSSEGPseudo 231 uint16_t LMUL : 3; member in struct:llvm::RISCV::VSXSEGPseudo 241 uint16_t LMUL : 3; member in struct:llvm::RISCV::VLEPseudo 249 uint16_t LMUL : 3; member in struct:llvm::RISCV::VSEPseudo 257 uint16_t LMUL : 3; member in struct:llvm::RISCV::VLX_VSXPseudo
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H A D | RISCVInsertVSETVLI.cpp | 227 bool LMUL = false; member in struct:__anon2610::DemandedFields 234 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy; 245 LMUL = true; 285 OS << "LMUL=" << LMUL << ", "; local 325 if (Used.LMUL && 375 // Loads and stores with implicit EEW do not demand SEW or LMUL directly. 377 // EMUL, but which allows us the flexibility to change SEW and LMUL 383 Res.LMUL = false; 398 Res.LMUL 999 isLMUL1OrSmaller(RISCVII::VLMUL LMUL) argument [all...] |
H A D | RISCVRegisterInfo.cpp | 277 // LMUL*VLENB bytes. 289 unsigned LMUL = ZvlssegInfo->second; local 290 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations."); 292 switch (LMUL) { 294 llvm_unreachable("LMUL must be 1, 2, or 4."); 319 int64_t Offset = VLENB * LMUL; 323 uint32_t ShiftAmount = Log2_32(LMUL); 354 // LMUL*VLENB bytes. 366 unsigned LMUL local [all...] |
H A D | RISCVISelDAGToDAG.cpp | 241 unsigned NF, RISCVII::VLMUL LMUL) { 254 switch (LMUL) { 256 llvm_unreachable("Invalid LMUL."); 346 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 353 SDValue Merge = createTuple(*CurDAG, Regs, NF, LMUL); 362 static_cast<unsigned>(LMUL)); 386 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 393 SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); 403 Log2SEW, static_cast<unsigned>(LMUL)); 428 RISCVII::VLMUL LMUL local 240 createTuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, unsigned NF, RISCVII::VLMUL LMUL) argument 483 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 513 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 1730 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 1783 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 1810 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 1928 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 1967 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local 2144 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); local [all...] |
H A D | RISCVInstrInfo.cpp | 232 // LMUL = 1/2/4/8. We should be able to convert vmv1r.v to vmv.v.v 233 // for fractional LMUL operations. However, we could not use the vsetvli 235 // 2 x LMUL. 251 // We only permit the source of COPY has the same LMUL as the defined 253 // There are cases we need to keep the whole register copy if the LMUL 269 // only checking the LMUL is insufficient due to reduction result is 310 llvm_unreachable("Impossible LMUL for vector register copy."); 2609 #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL) \ 2610 RISCV::PseudoV##OP##_##TYPE##_##LMUL 2771 #define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL) \ [all...] |
H A D | RISCVTargetTransformInfo.cpp | 26 "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " 274 unsigned LMUL = local 281 ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0); 286 ? LMUL * RISCV::RVVBitsPerBlock 519 // At low LMUL, most of the cost is producing the vrgather index register. 520 // At high LMUL, the cost of the vrgather itself will dominate.
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H A D | RISCVISelLowering.cpp | 165 // Disable the smallest fractional LMUL types if ELEN is less than 1454 // The maximum VF is for the smallest element width with LMUL=8. 2290 llvm_unreachable("Invalid LMUL."); 2311 llvm_unreachable("Invalid LMUL."); 2327 RISCVII::VLMUL LMUL = getLMUL(VT); local 2328 if (LMUL == RISCVII::VLMUL::LMUL_F8 || 2329 LMUL == RISCVII::VLMUL::LMUL_F4 || 2330 LMUL == RISCVII::VLMUL::LMUL_F2 || 2331 LMUL == RISCVII::VLMUL::LMUL_1) { 2336 if (LMUL 8324 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT); local 8339 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVBaseInfo.h | 149 /// \returns the LMUL for the instruction. 493 // Is this a LMUL value that can be encoded into the VTYPE format. 494 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { argument 495 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1); 509 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) { argument 510 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL"); 511 unsigned LmulLog2 = Log2_32(LMUL); [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 58 // Corresponds to LMUL instruction 59 LMUL,
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H A D | XCoreISelDAGToDAG.cpp | 198 case XCoreISD::LMUL: {
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H A D | XCoreISelLowering.cpp | 59 case XCoreISD::LMUL : return "XCoreISD::LMUL"; 556 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 1610 case XCoreISD::LMUL: { 1622 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), 1650 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, 1675 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
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/freebsd-current/contrib/llvm-project/clang/include/clang/Support/ |
H A D | RISCVVIntrinsicUtils.h | 235 // Exponential LMUL 239 // Return the C/C++ string representation of LMUL 256 LMULType LMUL; member in class:clang::RISCV::RVVType 362 /// and LMUL with type transformers). It also record result of type in legal 545 // Supported LMUL.
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/freebsd-current/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGDebugInfo.cpp | 804 unsigned LMUL; local 808 LMUL = 1; 812 LMUL = 64 / FixedSize; 814 LMUL = FixedSize / 64; 817 // Element count = (VLENB / SEW) x LMUL 827 llvm::dwarf::DW_OP_div, llvm::dwarf::DW_OP_constu, LMUL});
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