Searched refs:Imm (Results 1 - 25 of 304) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMatInt.h19 int64_t Imm; member in struct:llvm::LoongArchMatInt::Inst
20 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { argument
74 switch ((Imm >> 6) & 0x7) {
85 static inline unsigned getShiftValue(unsigned Imm) { argument
86 return Imm & 0x3f;
99 unsigned Imm) {
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
110 return (STEnc << 6) | (Imm & 0x3f);
118 static inline unsigned getArithShiftValue(unsigned Imm) { argument
119 return Imm
98 getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm) argument
123 getExtendType(unsigned Imm) argument
138 getArithExtendType(unsigned Imm) argument
170 getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm) argument
178 getMemDoShift(unsigned Imm) argument
184 getMemExtendType(unsigned Imm) argument
213 processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding) argument
343 getFPImmFloat(unsigned Imm) argument
367 getFP16Imm(const APInt &Imm) argument
393 getFP32Imm(const APInt &Imm) argument
421 getFP64Imm(const APInt &Imm) argument
451 isAdvSIMDModImmType1(uint64_t Imm) argument
456 encodeAdvSIMDModImmType1(uint64_t Imm) argument
460 decodeAdvSIMDModImmType1(uint8_t Imm) argument
466 isAdvSIMDModImmType2(uint64_t Imm) argument
471 encodeAdvSIMDModImmType2(uint64_t Imm) argument
475 decodeAdvSIMDModImmType2(uint8_t Imm) argument
481 isAdvSIMDModImmType3(uint64_t Imm) argument
486 encodeAdvSIMDModImmType3(uint64_t Imm) argument
490 decodeAdvSIMDModImmType3(uint8_t Imm) argument
496 isAdvSIMDModImmType4(uint64_t Imm) argument
501 encodeAdvSIMDModImmType4(uint64_t Imm) argument
505 decodeAdvSIMDModImmType4(uint8_t Imm) argument
511 isAdvSIMDModImmType5(uint64_t Imm) argument
517 encodeAdvSIMDModImmType5(uint64_t Imm) argument
521 decodeAdvSIMDModImmType5(uint8_t Imm) argument
527 isAdvSIMDModImmType6(uint64_t Imm) argument
533 encodeAdvSIMDModImmType6(uint64_t Imm) argument
537 decodeAdvSIMDModImmType6(uint8_t Imm) argument
543 isAdvSIMDModImmType7(uint64_t Imm) argument
548 encodeAdvSIMDModImmType7(uint64_t Imm) argument
552 decodeAdvSIMDModImmType7(uint8_t Imm) argument
558 isAdvSIMDModImmType8(uint64_t Imm) argument
563 decodeAdvSIMDModImmType8(uint8_t Imm) argument
568 encodeAdvSIMDModImmType8(uint64_t Imm) argument
573 isAdvSIMDModImmType9(uint64_t Imm) argument
579 encodeAdvSIMDModImmType9(uint64_t Imm) argument
583 decodeAdvSIMDModImmType9(uint8_t Imm) argument
593 isAdvSIMDModImmType10(uint64_t Imm) argument
635 encodeAdvSIMDModImmType10(uint64_t Imm) argument
663 decodeAdvSIMDModImmType10(uint8_t Imm) argument
677 isAdvSIMDModImmType11(uint64_t Imm) argument
684 encodeAdvSIMDModImmType11(uint64_t Imm) argument
712 decodeAdvSIMDModImmType11(uint8_t Imm) argument
727 isAdvSIMDModImmType12(uint64_t Imm) argument
733 encodeAdvSIMDModImmType12(uint64_t Imm) argument
761 decodeAdvSIMDModImmType12(uint8_t Imm) argument
777 isSVEMaskOfIdenticalElements(int64_t Imm) argument
784 isSVECpyImm(int64_t Imm) argument
807 isSVEAddSubImm(int64_t Imm) argument
814 isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp106 static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, argument
108 assert(isUInt<18>(Imm) && "Invalid immediate");
109 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2)));
113 static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, argument
115 assert(isUInt<18>(Imm) && "Invalid immediate");
116 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm)));
120 static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, argument
127 assert(isUInt<12>(Imm) && "Invalid immediate");
128 if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true,
130 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm)));
141 decodeL32ROperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
150 decodeImm8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
157 decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
165 decodeImm12Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
172 decodeUimm4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
179 decodeUimm5Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
186 decodeImm1_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
193 decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
203 decodeB4constOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
213 decodeB4constuOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
222 decodeMem8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
230 decodeMem16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
238 decodeMem32Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument
34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument
40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument
46 unsigned Shamt = llvm::countr_zero(Imm);
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument
129 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument
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H A DMipsAnalyzeImmediate.h26 /// Analyze - Get an instruction sequence to load immediate Imm. The last
29 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
38 /// load immediate Imm
39 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
42 /// load immediate Imm
43 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
46 /// load immediate Imm
47 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
49 /// GetInstSeqLs - Get instruction sequences to load immediate Imm.
50 void GetInstSeqLs(uint64_t Imm, unsigne
[all...]
H A DMipsISelDAGToDAG.h97 virtual bool selectVSplat(SDNode *N, APInt &Imm,
100 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
102 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
104 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
106 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
108 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
110 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
112 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
114 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
116 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons
137 getImm(const SDNode *Node, uint64_t Imm) argument
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H A DMipsSEISelDAGToDAG.h96 bool selectVSplat(SDNode *N, APInt &Imm,
99 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
102 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
104 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
106 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
108 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
110 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
112 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
114 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
116 bool selectVSplatSimm5(SDValue N, SDValue &Imm) cons
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H A DMipsISelDAGToDAG.cpp157 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, argument
163 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
168 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
173 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
178 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
183 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
188 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
193 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
198 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
203 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { argument
99 return ShOp | (Imm << 3);
106 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } argument
109 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } argument
111 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
115 inline unsigned getSOImmValRotate(unsigned Imm) { argument
118 if ((Imm & ~255U) == 0) return 0;
121 unsigned TZ = llvm::countr_zero(Imm);
210 getThumbImmValShift(unsigned Imm) argument
229 getThumbImm16ValShift(unsigned Imm) argument
263 unsigned u, Vs, Imm; local
328 isT2SOImmTwoPartVal(unsigned Imm) argument
355 getT2SOImmTwoPartFirst(unsigned Imm) argument
372 getT2SOImmTwoPartSecond(unsigned Imm) argument
631 getFPImmFloat(unsigned Imm) argument
654 getFP16Imm(const APInt &Imm) argument
679 getFP32FP16Imm(const APInt &Imm) argument
692 getFP32Imm(const APInt &Imm) argument
720 getFP64Imm(const APInt &Imm) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.h23 Imm, // LUI enumerator in enum:llvm::RISCVMatInt::OpndKind
30 int32_t Imm; // The largest value we need to store is 20 bits. member in class:llvm::RISCVMatInt::Inst
33 Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {
34 assert(I == Imm && "truncated");
38 int64_t getImm() const { return Imm; }
H A DRISCVInstPrinter.cpp123 unsigned Imm = MI->getOperand(OpNo).getImm(); local
124 auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
128 markup(O, Markup::Register) << formatImm(Imm);
174 unsigned Imm = MI->getOperand(OpNo).getImm(); local
175 if (Imm == 1) {
177 } else if (Imm == 30) {
179 } else if (Imm == 31) {
182 float FPVal = RISCVLoadFPImm::getFPImm(Imm);
207 unsigned Imm = MI->getOperand(OpNo).getImm(); local
210 if (RISCVVType::getVLMUL(Imm)
221 unsigned Imm = MI->getOperand(OpNo).getImm(); local
297 int64_t Imm = MI->getOperand(OpNo).getImm(); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.h31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
55 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
58 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
61 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm,
65 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
69 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm,
73 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm,
80 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
104 void DecodeBLENDMask(unsigned NumElts, unsigned Imm,
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H A DX86ShuffleDecode.cpp26 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument
34 unsigned ZMask = Imm & 15;
35 unsigned CountD = (Imm >> 4) & 3;
36 unsigned CountS = (Imm >> 6) & 3;
99 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, argument
106 if (i >= Imm) M = i - Imm + l;
111 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, argument
117 unsigned Base = i + Imm;
124 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, argument
138 DecodeVALIGNMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
147 DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
163 DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
177 DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
200 DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
263 decodeVSHUF64x2FamilyMask(unsigned NumElts, unsigned ScalarSize, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
280 DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
314 DecodeBLENDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
363 DecodeVPERMMask(unsigned NumElts, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp182 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
183 if (!isUInt<N>(Imm))
185 Inst.addOperand(MCOperand::createImm(Imm));
190 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
191 if (!isUInt<N>(Imm))
193 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
197 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
200 return decodeUImmOperand<1>(Inst, Imm);
203 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
206 return decodeUImmOperand<2>(Inst, Imm);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.h28 void expandMOVImm(uint64_t Imm, unsigned BitSize,
H A DAArch64ExpandImm.cpp22 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument
25 return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
124 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { argument
129 Imm &= ~(Mask << (Idx * 16));
132 Imm |= Mask << (Idx * 16);
134 return Imm;
373 static bool tryEorOfLogicalImmediates(uint64_t Imm, argument
376 // immediates, by finding the repetition size of Imm.
383 if ((Imm & Mask) != ((Imm >> BigSiz
466 expandMOVImmSimple(uint64_t Imm, unsigned BitSize, unsigned OneChunks, unsigned ZeroChunks, SmallVectorImpl<ImmInsnModel> &Insn) argument
525 expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl<ImmInsnModel> &Insn) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h52 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, argument
65 if (Imm == 0)
67 if (isInt<16>(Imm.getSExtValue()))
69 if (isInt<21>(Imm.getZExtValue()))
71 if (isInt<32>(Imm.getSExtValue())) {
72 if ((Imm.getSExtValue() & 0xFFFF) == 0)
81 const APInt &Imm, Type *Ty,
84 return getIntImmCost(Imm, Ty, CostKind);
88 const APInt &Imm, Type *Ty,
90 return getIntImmCost(Imm, T
80 getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst = nullptr) argument
87 getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp81 auto Imm = OffsetOp.getImm(); local
82 if (Imm >= 0)
83 O << " + " << formatImm(Imm);
85 O << " - " << formatImm(-Imm);
107 int32_t Imm = Op.getImm(); local
108 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
110 int16_t Imm = Op.getImm(); local
111 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
[all...]
H A DBPFMCTargetDesc.cpp82 int32_t Imm; variable
84 Imm = (short)Inst.getOperand(2).getImm();
87 Imm = (short)Inst.getOperand(0).getImm();
89 Imm = (int)Inst.getOperand(0).getImm();
93 Target = Addr + Size + Imm * Size;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp95 int64_t Imm = MO.getImm(); local
99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
107 if (Imm & NVPTX::PTXCvtMode::RELU_FLAG)
111 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
152 int64_t Imm = MO.getImm(); local
156 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
159 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
226 int Imm = (int) MO.getImm(); local
228 if (Imm)
277 int Imm = (int)MO.getImm(); local
279 O << Imm; // Just print out PTX version local
316 int64_t Imm = MO.getImm(); local
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp62 int64_t Imm = MI->getOperand(OpNo).getImm(); local
63 if (isInt<16>(Imm) || isUInt<16>(Imm))
64 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
100 uint32_t Imm = MI->getOperand(OpNo).getImm(); local
101 if (Imm != 0) {
108 O << formatDec(SignExtend32<24>(Imm));
117 uint32_t Imm = MI->getOperand(OpNo).getImm(); local
118 if (Imm != 0) {
127 O << formatDec(SignExtend32(Imm, AMDGP
178 auto Imm = MI->getOperand(OpNo).getImm(); local
451 printImmediateInt16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument
465 printImmediateFloat16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument
491 printImmediate16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument
508 printImmediateV216(uint32_t Imm, uint8_t OpType, const MCSubtargetInfo &STI, raw_ostream &O) argument
538 printImmediateFloat32(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument
568 printImmediate32(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O) argument
583 printImmediate64(uint64_t Imm, const MCSubtargetInfo &STI, raw_ostream &O, bool IsFP) argument
628 unsigned Imm = MI->getOperand(OpNo).getImm(); local
644 O << " blgp:" << Imm; local
650 unsigned Imm = MI->getOperand(OpNo).getImm(); local
660 unsigned Imm = MI->getOperand(OpNo).getImm(); local
991 unsigned Imm = MI->getOperand(OpNo).getImm(); local
1004 unsigned Imm = MI->getOperand(OpNo).getImm(); local
1110 unsigned Imm = MI->getOperand(OpNo).getImm(); local
1119 unsigned Imm = MI->getOperand(OpNo).getImm(); local
1129 unsigned Imm = MI->getOperand(OpNo).getImm(); local
1169 unsigned Imm = MI->getOperand(OpNo).getImm(); local
1369 auto Imm = MI->getOperand(OpNo).getImm() & 0x7; local
1379 auto Imm = MI->getOperand(OpNo).getImm() & 0x7; local
1389 unsigned Imm = MI->getOperand(OpNum).getImm(); local
1401 O << "invalid_param_" << Imm; local
1473 int Imm = MI->getOperand(OpNo).getImm(); local
[all...]
/freebsd-current/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_hexagon.cpp43 encodeExtendedTransferImmediate(uint32_t Imm, RegNum DestReg,
49 Imm = Imm & 0x03f;
52 return PO_TFR_IMM | ParseBits | (Imm << 5) | (DestReg & REG_MASK);
56 encodeConstantExtender(uint32_t Imm) XRAY_NEVER_INSTRUMENT {
68 Imm = Imm >> 6;
70 const uint32_t high = (Imm & IMM_MASK_HIGH) << 16;
71 const uint32_t low = Imm & IMM_MASK_LOW;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, argument
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, argument
75 int32_t Offset = SignExtend32<24>(Imm);
248 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, argument
251 if (!isUInt<N>(Imm))
253 Inst.addOperand(MCOperand::createImm(Imm));
258 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, argument
261 if (!isUInt<N>(Imm))
263 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
267 decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
285 decodeDispRIXOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
293 decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
306 decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
314 decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
325 decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
336 decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
346 decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMIRFormatter.h44 std::optional<unsigned> OpIdx, int64_t Imm) const {
45 OS << Imm; local
51 StringRef Src, int64_t &Imm,
50 parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, StringRef Src, int64_t &Imm, ErrorCallbackType ErrorCallback) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCTargetDesc.cpp107 int64_t Imm = Inst.getOperand(0).getImm(); variable
108 Target = Addr + Size + Imm;
111 int64_t Imm = Inst.getOperand(0).getImm(); variable
115 if (Imm == 0)
118 Target = Imm;

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