Searched refs:FP64 (Results 1 - 9 of 9) sorted by relevance

/freebsd-current/contrib/llvm-project/clang/lib/Basic/Targets/
H A DMips.cpp143 case FP64:
148 if (FPMode == FP64 || IsSingleFloat)
221 .Case("fp64", FPMode == FP64)
259 if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
265 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
271 if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
H A DMips.h59 enum FPModeEnum { FPXX, FP32, FP64 } FPMode; enumerator in enum:clang::targets::MipsTargetInfo::FPModeEnum
318 FPMode = isFP64Default() ? FP64 : FPXX;
340 FPMode = FP64;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.h119 bool FP64) const;
122 bool FP64) const;
H A DMipsSEFrameLowering.cpp85 MachineBasicBlock::iterator I, bool FP64) const;
87 MachineBasicBlock::iterator I, bool FP64) const;
288 bool FP64) const {
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
344 bool FP64) const {
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
H A DMipsSEInstrInfo.cpp754 bool FP64) const {
768 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
786 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
787 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
796 bool isMicroMips, bool FP64) const {
822 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
842 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
843 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.cpp48 WebAssembly::FP64})
148 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
H A DWebAssemblyFrameLowering.cpp189 ? WebAssembly::FP64
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600Subtarget.h39 bool FP64 = false; member in class:llvm::final
H A DGCNSubtarget.h100 bool FP64 = false; member in class:llvm::final
340 return FP64;
348 return FP64;

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