Searched refs:DstLo (Results 1 - 9 of 9) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); local
110 PairedCopy(TII, MBB, MI, MI.getDebugLoc(), DstHi, DstLo, Hi, Lo);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1851 auto DstLo = MRI.createGenericVirtualRegister(s64); local
1900 MIRBuilder.buildExtract({DstLo}, {CASDst}, 0);
1925 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch},
1936 MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), {DstLo, DstHi});
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); local
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
H A DMipsSEInstrInfo.cpp717 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); local
719 LoInst.addReg(DstLo, RegState::Define);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1585 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0); local
1588 MRI.setRegBank(DstLo, AMDGPU::SGPRRegBank);
1645 DstLo = B.buildCopy(S32, DstLo).getReg(0);
1647 MRI.setRegBank(DstLo, AMDGPU::VGPRRegBank);
1665 auto AddLo = B.buildUAddo(S32, CarryType, DstLo, Src2Lo);
1666 DstLo = AddLo.getReg(0);
1668 MRI.setRegBank(DstLo, DstBank);
1691 B.buildMergeLikeInstr(Dst0, {DstLo, DstHi});
H A DAMDGPUInstructionSelector.cpp376 Register DstLo = MRI->createVirtualRegister(&HalfRC); local
380 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
390 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_CO_U32_e64), DstLo)
407 .addReg(DstLo)
H A DSIInstrInfo.cpp2129 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
2157 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
2179 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
2204 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
2209 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstLo)
H A DSIISelLowering.cpp5052 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
5081 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
5095 .addReg(DstLo)
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1949 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); local
1960 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)

Completed in 358 milliseconds