Searched refs:Dst0Reg (Results 1 - 3 of 3) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2094 Register Dst0Reg = MI.getOperand(0).getReg(); local
2095 LLT Dst0Ty = MRI.getType(Dst0Reg);
2098 Builder.buildCast(Dst0Reg, MIB);
2100 Builder.buildTrunc(Dst0Reg, SrcReg);
2107 Register Dst0Reg = MI.getOperand(0).getReg(); local
2108 LLT Dst0Ty = MRI.getType(Dst0Reg);
2134 Register Dst0Reg = MI.getOperand(0).getReg(); local
2142 LLT Dst0Ty = MRI.getType(Dst0Reg);
2148 Builder.buildZExt(Dst0Reg, ZExtSrcReg);
2152 replaceRegWith(MRI, Dst0Reg, ZExtSrcRe
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H A DLegalizerHelper.cpp1913 Register Dst0Reg = MI.getOperand(0).getReg();
1914 LLT DstTy = MRI.getType(Dst0Reg);
1943 MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
7092 Register Dst0Reg = MI.getOperand(0).getReg();
7093 LLT DstTy = MRI.getType(Dst0Reg);
7104 MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp425 Register Dst0Reg = I.getOperand(0).getReg(); local
453 auto CarryInst = BuildMI(*BB, &I, DL, TII.get(HasCarryIn ? CarryOpc : NoCarryOpc), Dst0Reg)
466 if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) ||

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