/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TileShapeInfo.h | 72 for (const MachineOperand &DefMO : MRI->def_operands(Reg)) { 73 const auto *MI = DefMO.getParent();
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LiveRangeShrink.cpp | 168 const MachineOperand *DefMO = nullptr; local 189 if (DefMO) { 193 DefMO = &MO; 194 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO && 195 MRI.getRegClass(DefMO->getReg()) == 220 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
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H A D | CodeGenCommonISel.cpp | 257 for (auto *DefMO : DbgUsers) { 258 MachineInstr *DbgMI = DefMO->getParent(); 263 int UseMOIdx = DbgMI->findRegisterUseOperandIdx(DefMO->getReg()); 264 assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) &&
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H A D | FixupStatepointCallerSaved.cpp | 486 MachineOperand &DefMO = MI.getOperand(I); local 487 assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand"); 488 Register Reg = DefMO.getReg(); 489 assert(DefMO.isTied() && "Def is expected to be tied");
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H A D | MachineFunction.cpp | 1193 for (const auto &DefMO : DefMI.operands()) { 1194 if (DefMO.isReg() && DefMO.isDef() && DefMO.getReg() == Reg)
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H A D | MachineLICM.cpp | 1125 MachineOperand &DefMO = MI.getOperand(i); local 1126 if (!DefMO.isReg() || !DefMO.isDef()) 1129 Register Reg = DefMO.getReg();
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H A D | ModuloSchedule.cpp | 1616 for (MachineOperand &DefMO : MI->defs()) { 1618 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { 1627 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, 1930 for (MachineOperand &DefMO : MI->defs()) { 1932 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { 1941 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0,
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H A D | ScheduleDAGInstrs.cpp | 318 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); local 320 (Kind != SDep::Output || !MO.isDead() || !DefMO.isDead())) { 321 SDep Dep(SU, Kind, DefMO.getReg());
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H A D | MachineInstr.cpp | 1122 MachineOperand &DefMO = getOperand(DefIdx); local 1124 assert(DefMO.isDef() && "DefIdx must be a def operand"); 1126 assert(!DefMO.isTied() && "Def is already tied to another use"); 1142 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
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H A D | RegisterCoalescer.cpp | 1384 MachineOperand &DefMO = NewMI.getOperand(0); local 1385 if (DefMO.getSubReg() == DstIdx) { 1405 DefMO.setIsUndef(false); // Only subregs can have def+undef.
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRVVInitUndef.cpp | 133 return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) { 134 return DefMO.isReg() && DefMO.isEarlyClobber();
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyExplicitLocals.cpp | 199 for (MachineOperand &DefMO : Def->explicit_uses()) { 200 if (!DefMO.isReg()) 202 return findStartOfTree(DefMO, MRI, MFI);
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H A D | WebAssemblyRegStackify.cpp | 648 MachineOperand &DefMO = Def->getOperand(0); local 652 .addReg(DefReg, getUndefRegState(DefMO.isDead()));
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPeepholeSDWA.cpp | 296 for (auto &DefMO : DefInstr->defs()) { 297 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) 298 return &DefMO;
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H A D | SIInsertWaitcnts.cpp | 864 MachineOperand &DefMO = Inst.getOperand(I); 865 if (DefMO.isReg() && DefMO.isDef() && 866 TRI->isVGPR(*MRI, DefMO.getReg())) { 868 TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)),
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H A D | SIInstrInfo.h | 997 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would 1001 const MachineOperand &DefMO) const { 1007 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 452 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
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H A D | ARMBaseInstrInfo.cpp | 4369 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); local 4370 Register Reg = DefMO.getReg(); 4392 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, 4399 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, 4427 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) 4396 getOperandLatencyImpl( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 4304 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); local 4306 if (DefMO.isReg() && DefMO.getReg().isPhysical()) { 4307 if (DefMO.isImplicit()) { 4308 for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) {
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 177 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); local 178 Register Reg = DefMO.getReg();
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