Searched refs:DefMO (Results 1 - 20 of 20) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTileShapeInfo.h72 for (const MachineOperand &DefMO : MRI->def_operands(Reg)) {
73 const auto *MI = DefMO.getParent();
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeShrink.cpp168 const MachineOperand *DefMO = nullptr; local
189 if (DefMO) {
193 DefMO = &MO;
194 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO &&
195 MRI.getRegClass(DefMO->getReg()) ==
220 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
H A DCodeGenCommonISel.cpp257 for (auto *DefMO : DbgUsers) {
258 MachineInstr *DbgMI = DefMO->getParent();
263 int UseMOIdx = DbgMI->findRegisterUseOperandIdx(DefMO->getReg());
264 assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) &&
H A DFixupStatepointCallerSaved.cpp486 MachineOperand &DefMO = MI.getOperand(I); local
487 assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand");
488 Register Reg = DefMO.getReg();
489 assert(DefMO.isTied() && "Def is expected to be tied");
H A DMachineFunction.cpp1193 for (const auto &DefMO : DefMI.operands()) {
1194 if (DefMO.isReg() && DefMO.isDef() && DefMO.getReg() == Reg)
H A DMachineLICM.cpp1125 MachineOperand &DefMO = MI.getOperand(i); local
1126 if (!DefMO.isReg() || !DefMO.isDef())
1129 Register Reg = DefMO.getReg();
H A DModuloSchedule.cpp1616 for (MachineOperand &DefMO : MI->defs()) {
1618 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
1627 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0,
1930 for (MachineOperand &DefMO : MI->defs()) {
1932 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
1941 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0,
H A DScheduleDAGInstrs.cpp318 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); local
320 (Kind != SDep::Output || !MO.isDead() || !DefMO.isDead())) {
321 SDep Dep(SU, Kind, DefMO.getReg());
H A DMachineInstr.cpp1122 MachineOperand &DefMO = getOperand(DefIdx); local
1124 assert(DefMO.isDef() && "DefIdx must be a def operand");
1126 assert(!DefMO.isTied() && "Def is already tied to another use");
1142 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
H A DRegisterCoalescer.cpp1384 MachineOperand &DefMO = NewMI.getOperand(0); local
1385 if (DefMO.getSubReg() == DstIdx) {
1405 DefMO.setIsUndef(false); // Only subregs can have def+undef.
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRVVInitUndef.cpp133 return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
134 return DefMO.isReg() && DefMO.isEarlyClobber();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp199 for (MachineOperand &DefMO : Def->explicit_uses()) {
200 if (!DefMO.isReg())
202 return findStartOfTree(DefMO, MRI, MFI);
H A DWebAssemblyRegStackify.cpp648 MachineOperand &DefMO = Def->getOperand(0); local
652 .addReg(DefReg, getUndefRegState(DefMO.isDead()));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp296 for (auto &DefMO : DefInstr->defs()) {
297 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())
298 return &DefMO;
H A DSIInsertWaitcnts.cpp864 MachineOperand &DefMO = Inst.getOperand(I);
865 if (DefMO.isReg() && DefMO.isDef() &&
866 TRI->isVGPR(*MRI, DefMO.getReg())) {
868 TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)),
H A DSIInstrInfo.h997 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
1001 const MachineOperand &DefMO) const {
1007 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h452 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
H A DARMBaseInstrInfo.cpp4369 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); local
4370 Register Reg = DefMO.getReg();
4392 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4399 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
4427 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4396 getOperandLatencyImpl( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp4304 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); local
4306 if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
4307 if (DefMO.isImplicit()) {
4308 for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp177 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); local
178 Register Reg = DefMO.getReg();

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