Searched refs:Cycles (Results 1 - 25 of 31) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp42 // Cycles - Number of cycles until return if HasReturn is true, otherwise
44 unsigned int Cycles = 0; member in struct:__anon2701::VisitedBBInfo
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles) argument
48 : HasReturn(HasReturn), Cycles(Cycles) {}
75 unsigned int Cycles = 0);
78 unsigned int &Cycles);
133 unsigned Cycles = ReturnBB.second; local
140 if (Cycles < Threshold) {
152 addPadding(MBB, ReturnLoc, Threshold - Cycles);
163 findReturns(MachineBasicBlock *MBB, unsigned int Cycles) argument
184 cyclesUntilReturn(MachineBasicBlock *MBB, unsigned int &Cycles) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp22 unsigned Cycles) {
25 CRD.Cycles = Cycles;
26 DependentWriteCyclesLeft = Cycles;
31 unsigned Cycles) {
41 if (TotalCycles < Cycles) {
44 CRD.Cycles = Cycles;
45 TotalCycles = Cycles;
127 << getRegisterID() << ", Cycles Lef
21 writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles) argument
30 writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles) argument
[all...]
H A DPipeline.cpp46 ++Cycles;
49 return Cycles;
97 LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n');
103 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n");
H A DInstrBuilder.cpp346 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles);
374 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles);
/freebsd-current/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp32 unsigned Cycles = Resource.second.size(); local
41 std::make_pair(ResourceUnit, ReleaseAtCycles(Cycles, NumUnits)));
48 // Uniformly distribute Cycles across all of the units.
57 ReleaseAtCycles(Cycles, NumUnits * SubUnit.NumUnits)));
H A DInOrderIssueStage.cpp30 void StallInfo::update(const InstRef &Inst, unsigned Cycles, StallKind SK) { argument
32 CyclesLeft = Cycles;
119 if (unsigned Cycles = checkRegisterHazard(PRF, STI, IR)) {
120 SI.update(IR, Cycles, StallInfo::StallKind::REGISTER_DEPS);
/freebsd-current/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h87 int16_t Cycles; member in struct:llvm::MCWriteLatencyEntry
91 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
106 int Cycles; member in struct:llvm::MCReadAdvanceEntry
110 && Cycles == Other.Cycles;
H A DMCSubtargetInfo.h197 return I->Cycles;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp113 DelayInfo(DelayType Type, unsigned Cycles) { argument
118 VALUCycles = Cycles;
122 TRANSCycles = Cycles;
129 SALUCycles = std::min(Cycles, SALU_CYCLES_MAX);
155 // a TRANS, else 0. Cycles is the number of cycles it takes to issue the
157 bool advance(DelayType Type, unsigned Cycles) { argument
161 if (VALUNum >= VALU_MAX || VALUCycles <= Cycles) {
167 VALUCycles -= Cycles;
173 if (TRANSNum >= TRANS_MAX || TRANSCycles <= Cycles) {
180 TRANSCycles -= Cycles;
230 advance(DelayType Type, unsigned Cycles) argument
400 unsigned Cycles = SIInstrInfo::getNumWaitStates(MI); local
[all...]
H A DR600InstrInfo.cpp382 unsigned Cycles[3] = { 2, 1, 0};
383 return Cycles[Op];
386 unsigned Cycles[3] = { 1, 2, 2};
387 return Cycles[Op];
390 unsigned Cycles[3] = { 2, 1, 2};
391 return Cycles[Op];
394 unsigned Cycles[3] = { 2, 2, 1};
395 return Cycles[Op];
/freebsd-current/contrib/llvm-project/llvm/include/llvm/MCA/
H A DSupport.h56 ReleaseAtCycles(unsigned Cycles, unsigned ResourceUnits = 1) argument
57 : Numerator(Cycles), Denominator(ResourceUnits) {}
H A DPipeline.h64 unsigned Cycles = 0; member in class:llvm::mca::Pipeline
H A DInstruction.h188 unsigned Cycles; member in struct:llvm::mca::CriticalDependency
303 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
375 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
419 void subtract(unsigned Cycles) { argument
420 assert(End >= Cycles);
421 End -= Cycles;
439 ResourceUsage(CycleSegment Cycles, unsigned Units = 1) argument
440 : CS(Cycles), NumUnits(Units) {}
/freebsd-current/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h119 unsigned Cycles = IR.getInstruction()->getCyclesLeft(); local
120 if (CriticalPredecessor.Cycles < Cycles) {
122 CriticalPredecessor.Cycles = Cycles;
184 if (isWaiting() && CriticalPredecessor.Cycles)
185 CriticalPredecessor.Cycles--;
/freebsd-current/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DTimelineView.cpp22 unsigned Cycles)
24 MaxCycle(Cycles == 0 ? std::numeric_limits<unsigned>::max() : Cycles),
121 static void tryChangeColor(raw_ostream &OS, unsigned Cycles, argument
126 raw_ostream::Colors Color = chooseColor(Cycles, Executions, BufferSize);
257 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) { argument
259 if (Cycles >= 10) {
261 for (unsigned I = 0; I <= Cycles; ++I) {
272 for (unsigned I = 0; I <= Cycles; ++I) {
20 TimelineView(const MCSubtargetInfo &sti, MCInstPrinter &Printer, llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations, unsigned Cycles) argument
H A DTimelineView.h167 unsigned Cycles);
H A DBottleneckAnalysis.cpp506 unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID);
513 addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles);
519 if (RegDep.Cycles) {
520 Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID);
522 addRegisterDep(From, To, RegDep.RegID, Cycles);
526 if (MemDep.Cycles) {
527 Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID);
529 addMemoryDep(From, To, Cycles);
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp51 if (WLEntry->Cycles < 0)
52 return WLEntry->Cycles;
53 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
165 DelayCycles = std::min(DelayCycles, E.Cycles);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp857 struct Cycles { struct in namespace:__anon1853
861 template <typename Remark> Remark &operator<<(Remark &R, Cycles C) {
936 << Cycles{"ResLength", ResLength}
938 << Cycles{"MinCrit", MinCrit} << ") by more than the threshold of "
939 << Cycles{"CritLimit", CritLimit}
1022 << Cycles{"CondCycles", Cond.Extra} << " to the critical path";
1025 << Cycles{"ShortCycles", Short.Extra};
1028 << Cycles{"LongCycles", Long.Extra};
1030 << Cycles{"CritLimit", CritLimit} << ".";
1038 << Cycles{"CondCycle
1169 unsigned Cycles = 0; local
[all...]
H A DTargetSchedule.cpp114 static unsigned capLatency(int Cycles) { argument
115 return Cycles >= 0 ? Cycles : 1000;
208 unsigned Latency = capLatency(WLEntry->Cycles);
H A DMachineTraceMetrics.cpp601 Cycles.erase(&I);
788 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
813 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
821 InstrCycles &MICycles = Cycles[&UseMI];
1090 unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0;
1126 InstrCycles &MICycles = Cycles[&MI];
1241 unsigned Cycles = 0;
1251 Cycles += (PI->ReleaseAtCycle *
1255 return Cycles;
/freebsd-current/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h50 void update(const InstRef &Inst, unsigned Cycles, StallKind SK);
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h308 return TE.Cycles.lookup(&MI);
334 DenseMap<const MachineInstr*, InstrCycles> Cycles; member in class:llvm::MachineTraceMetrics::Ensemble
404 // Cycles consumed on each processor resource per block.
/freebsd-current/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp356 int Cycles = Stage->getValueAsInt("Cycles"); local
357 ItinString += " { " + itostr(Cycles) + ", ";
1122 WLEntry.Cycles = 0;
1143 WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
1274 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
1357 OS << "\n// {Cycles, WriteResourceID}\n"
1364 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
1373 OS << "\n// {UseIdx, WriteResourceID, Cycles}\
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp223 Latency = std::max(Latency, WLEntry->Cycles);

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