/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixVGPRCopies.cpp | 64 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTOCRegDeps.cpp | 121 MI.addOperand(MachineOperand::CreateReg(TOCReg,
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H A D | PPCPreEmitPeephole.cpp | 339 MachineOperand::CreateReg(Pair->UseReg, true, true); 341 MachineOperand::CreateReg(Pair->UseReg, false, true);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInsertReadWriteCSR.cpp | 81 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
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H A D | RISCVInsertWriteVXRM.cpp | 383 MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, 77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, 85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 212 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 219 MI.addOperand(MachineOperand::CreateReg(
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H A D | HexagonHardwareLoops.cpp | 1892 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true)); 1903 MachineOperand MO = MachineOperand::CreateReg(PredR, false); 1918 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 217 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
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H A D | ARMBaseInstrInfo.h | 547 MachineOperand::CreateReg(PredReg, false)}}; 553 return MachineOperand::CreateReg(CCReg, false); 560 return MachineOperand::CreateReg(ARM::CPSR,
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H A D | ARMSLSHardening.cpp | 353 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/,
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H A D | Thumb2InstrInfo.cpp | 583 MI.addOperand(MachineOperand::CreateReg(0, false)); 615 MI.addOperand(MachineOperand::CreateReg(0, false));
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | FunctionLoweringInfo.h | 212 Register CreateReg(MVT VT, bool isDivergent = false);
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 636 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); 684 Ops.push_back(MachineOperand::CreateReg( 795 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); 844 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); 850 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); 863 Ops.push_back(MachineOperand::CreateReg( 869 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, 897 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), 899 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), 916 Ops.push_back(MachineOperand::CreateReg(getRegForValu [all...] |
H A D | FunctionLoweringInfo.cpp | 363 /// CreateReg - Allocate a single virtual register for the given type. 364 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { function in class:FunctionLoweringInfo 385 Register R = CreateReg(RegisterVT, isDivergent);
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LiveVariables.cpp | 241 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 252 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, 263 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 371 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, 387 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
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H A D | MachineOutliner.cpp | 953 MachineOperand::CreateReg(I, true, /* isDef = true */ 959 MachineOperand::CreateReg(I, false, /* isDef = false */
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H A D | MachineInstr.cpp | 89 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true)); 91 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true)); 1983 addOperand(MachineOperand::CreateReg(IncomingReg, 2049 addOperand(MachineOperand::CreateReg(Reg, 2086 addOperand(MachineOperand::CreateReg(Reg,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCOptAddrMode.cpp | 470 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); 473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/ |
H A D | MSP430AsmParser.cpp | 200 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon2509::MSP430Operand 454 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc));
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SLSHardening.cpp | 370 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
H A D | VEAsmParser.cpp | 599 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon2664::VEOperand 1475 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1)); 1476 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2)); 1533 Op = VEOperand::CreateReg(Reg, S, E);
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CSEInfo.cpp | 373 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false));
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
H A D | AVRAsmParser.cpp | 213 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon2397::AVROperand 415 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegStackify.cpp | 84 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, 90 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,
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