Searched refs:CreateReg (Results 1 - 25 of 75) sorted by relevance

123

/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixVGPRCopies.cpp64 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp121 MI.addOperand(MachineOperand::CreateReg(TOCReg,
H A DPPCPreEmitPeephole.cpp339 MachineOperand::CreateReg(Pair->UseReg, true, true);
341 MachineOperand::CreateReg(Pair->UseReg, false, true);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertReadWriteCSR.cpp81 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
H A DRISCVInsertWriteVXRM.cpp383 MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp212 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
219 MI.addOperand(MachineOperand::CreateReg(
H A DHexagonHardwareLoops.cpp1892 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
1903 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
1918 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp217 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
H A DARMBaseInstrInfo.h547 MachineOperand::CreateReg(PredReg, false)}};
553 return MachineOperand::CreateReg(CCReg, false);
560 return MachineOperand::CreateReg(ARM::CPSR,
H A DARMSLSHardening.cpp353 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/,
H A DThumb2InstrInfo.cpp583 MI.addOperand(MachineOperand::CreateReg(0, false));
615 MI.addOperand(MachineOperand::CreateReg(0, false));
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h212 Register CreateReg(MVT VT, bool isDivergent = false);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp636 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
684 Ops.push_back(MachineOperand::CreateReg(
795 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true));
844 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
850 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
863 Ops.push_back(MachineOperand::CreateReg(
869 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true,
897 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
899 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
916 Ops.push_back(MachineOperand::CreateReg(getRegForValu
[all...]
H A DFunctionLoweringInfo.cpp363 /// CreateReg - Allocate a single virtual register for the given type.
364 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { function in class:FunctionLoweringInfo
385 Register R = CreateReg(RegisterVT, isDivergent);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp241 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
252 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
263 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
371 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
387 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
H A DMachineOutliner.cpp953 MachineOperand::CreateReg(I, true, /* isDef = true */
959 MachineOperand::CreateReg(I, false, /* isDef = false */
H A DMachineInstr.cpp89 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true));
91 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true));
1983 addOperand(MachineOperand::CreateReg(IncomingReg,
2049 addOperand(MachineOperand::CreateReg(Reg,
2086 addOperand(MachineOperand::CreateReg(Reg,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp470 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true));
473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp200 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon2509::MSP430Operand
454 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp370 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp599 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon2664::VEOperand
1475 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1));
1476 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2));
1533 Op = VEOperand::CreateReg(Reg, S, E);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp373 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp213 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon2397::AVROperand
415 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp84 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,
90 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,

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