Searched refs:CondCycles (Results 1 - 8 of 8) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp115 int CondCycles = 0, TCycles = 0, FCycles = 0; member in struct:__anon1850::SSAIfConv::PHIInfo
530 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,
972 unsigned CondDepth = adjCycles(BranchDepth, PI.CondCycles);
1022 << Cycles{"CondCycles", Cond.Extra} << " to the critical path";
1038 << Cycles{"CondCycles", Cond.Extra} << " to the critical path";
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h896 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
905 /// @param CondCycles Latency from Cond+Branch to select output.
911 int &CondCycles, int &TrueCycles,
908 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp553 Register FalseReg, int &CondCycles,
574 CondCycles = 2;
550 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Pred, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h367 Register TrueReg, Register FalseReg, int &CondCycles,
H A DSIInstrInfo.cpp3173 Register FalseReg, int &CondCycles,
3184 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
3204 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp701 Register FalseReg, int &CondCycles,
725 CondCycles = 1 + ExtraCondLat;
738 CondCycles = 5 + ExtraCondLat;
698 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1508 Register FalseReg, int &CondCycles,
1544 CondCycles = 1;
1505 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp3996 Register FalseReg, int &CondCycles,
4020 CondCycles = 2;

Completed in 297 milliseconds