| /freebsd-current/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegisterInfo.cpp | 24 BitVector SPIRVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
25 return BitVector(getNumRegs());
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| H A D | SPIRVRegisterInfo.h | 26 BitVector getReservedRegs(const MachineFunction &MF) const override;
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | CodeGenCoverage.h | 14 #include "llvm/ADT/BitVector.h"
21 BitVector RuleCoverage;
24 using const_covered_iterator = BitVector::const_set_bits_iterator;
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| H A D | Program.h | 26 class BitVector;
140 BitVector *AffinityMask = nullptr ///< CPUs or processors the new
155 BitVector *AffinityMask = nullptr);
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| /freebsd-current/contrib/llvm-project/clang/include/clang/Analysis/Analyses/ |
| H A D | ReachableCode.h | 23 class BitVector;
59 llvm::BitVector &Reachable);
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| H A D | CFGReachabilityAnalysis.h | 18 #include "llvm/ADT/BitVector.h"
32 using ReachableSet = llvm::BitVector;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiFrameLowering.h | 20 class BitVector;
49 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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| H A D | LanaiRegisterInfo.h | 33 BitVector getReservedRegs(const MachineFunction &MF) const override;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600RegisterInfo.h | 29 BitVector getReservedRegs(const MachineFunction &MF) const override;
54 void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
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| /freebsd-current/contrib/llvm-project/llvm/tools/llvm-pdbutil/ |
| H A D | TypeReferenceTracker.h | 12 #include "llvm/ADT/BitVector.h"
56 BitVector TypeReferenced;
57 BitVector IdReferenced;
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| H A D | PrettyClassDefinitionDumper.h | 12 #include "llvm/ADT/BitVector.h"
21 class BitVector;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFRegisterInfo.h | 29 BitVector getReservedRegs(const MachineFunction &MF) const override;
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| H A D | BPFFrameLowering.cpp | 32 BitVector &SavedRegs,
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | SpillPlacement.h | 37 class BitVector;
51 BitVector *ActiveNodes = nullptr;
108 void prepare(BitVector &RegBundles);
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| H A D | CriticalAntiDepBreaker.h | 18 #include "llvm/ADT/BitVector.h"
46 const BitVector AllocatableSet;
71 BitVector KeepRegs;
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | LiveRangeCalc.h | 27 #include "llvm/ADT/BitVector.h"
63 BitVector Seen;
76 using EntryInfoMap = DenseMap<LiveRange *, std::pair<BitVector, BitVector>>;
130 MachineBasicBlock &MBB, BitVector &DefOnEntry,
131 BitVector &UndefOnEntry);
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| H A D | LiveRegUnits.h | 17 #include "llvm/ADT/BitVector.h"
32 BitVector Units;
144 void addUnits(const BitVector &RegUnits) {
148 void removeUnits(const BitVector &RegUnits) {
152 const BitVector &getBitVector() const {
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| H A D | DetectDeadLanes.h | 31 #include "llvm/ADT/BitVector.h"
111 BitVector WorklistMembers;
114 BitVector DefinedByCopy;
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | StackLifetime.h | 13 #include "llvm/ADT/BitVector.h"
39 /// Each bit in the BitVector represents the liveness property
46 BitVector Begin;
49 BitVector End;
52 BitVector LiveIn;
55 BitVector LiveOut;
64 BitVector Bits;
113 BitVector InterestingAllocas;
169 static inline raw_ostream &operator<<(raw_ostream &OS, const BitVector &V) {
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | BitVector.h | 1 //===- llvm/ADT/BitVector.h - Bit vectors -----------------------*- C++ -*-===//
10 /// This file implements the BitVector class.
82 class BitVector { class in namespace:llvm
105 reference(BitVector &b, unsigned Idx) {
131 typedef const_set_bits_iterator_impl<BitVector> const_set_bits_iterator;
144 /// BitVector default ctor - Creates an empty bitvector.
145 BitVector() = default;
147 /// BitVector ctor - Creates a bitvector of specified number of bits. All
149 explicit BitVector(unsigned s, bool t = false) function in class:llvm::BitVector
351 BitVector
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VERegisterInfo.h | 32 BitVector getReservedRegs(const MachineFunction &MF) const override;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.h | 30 BitVector getReservedRegs(const MachineFunction &MF) const override;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.h | 31 BitVector getReservedRegs(const MachineFunction &MF) const override;
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| /freebsd-current/contrib/llvm-project/clang/include/clang/Analysis/FlowSensitive/ |
| H A D | ControlFlowContext.h | 21 #include "llvm/ADT/BitVector.h"
64 llvm::BitVector BlockReachable)
73 llvm::BitVector BlockReachable;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 25 #include "llvm/ADT/BitVector.h"
100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
127 void getSubRegs(unsigned Reg, BitVector &SRs) const;
128 void expandReg(unsigned Reg, BitVector &Set) const;
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
130 BitVector &Uses) const;
146 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {
151 void HexagonGenMux::expandReg(unsigned Reg, BitVector
[all...] |