Searched refs:locs (Results 1 - 17 of 17) sorted by relevance

/freebsd-9.3-release/contrib/gcc/
H A Dcselib.c252 for (l = v->locs; l; l = l->next)
283 && (! only_useless || CSELIB_VAL_PTR (x)->locs == 0))
307 struct elt_loc_list **p = &v->locs;
308 int had_locs = v->locs != 0;
318 if (had_locs && v->locs == 0)
333 if (v->locs == 0)
364 if (v->locs)
431 for (l = e->locs; l; l = l->next)
450 for (l = e->locs; l; l = l->next)
758 e->locs
[all...]
H A Dcselib.h37 struct elt_loc_list *locs; local
H A Dtree-ssa-loop-im.c124 struct mem_ref_loc *locs; /* The locations where it is found. */ member in struct:mem_ref
1127 for (aref = ref->locs; aref; aref = aref->next)
1145 schedule_sm (loop, exits, n_exits, ref->mem, ref->locs);
1264 ref->locs = NULL;
1276 record_mem_ref_loc (&ref->locs, stmt, mem);
1342 free_mem_ref_locs (ref->locs);
H A Dalias.c1408 for (l = val->locs; l; l = l->next)
1584 for (l = v->locs; l; l = l->next)
1587 for (l = v->locs; l; l = l->next)
1590 if (v->locs)
1591 return v->locs->loc;
H A Dpostreload.c270 for (l = val->locs; l; l = l->next)
477 for (l = v->locs; l; l = l->next)
H A Dgcse.c3078 for (l = val->locs; l; l = l->next)
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DCallingConvLower.cpp27 const TargetMachine &tm, SmallVectorImpl<CCValAssign> &locs,
30 TRI(*TM.getRegisterInfo()), Locs(locs), Context(C),
26 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf, const TargetMachine &tm, SmallVectorImpl<CCValAssign> &locs, LLVMContext &C) argument
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp28 SmallVectorImpl<CCValAssign> &locs,
30 : CallingConv(CC), IsVarArg(isVarArg), TM(tm), Locs(locs), Context(c) {
26 Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &tm, SmallVectorImpl<CCValAssign> &locs, LLVMContext &c) argument
H A DHexagonCallingConvLower.h58 SmallVectorImpl<CCValAssign> &locs, LLVMContext &c);
H A DHexagonISelLowering.cpp52 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
54 : CCState(CC, isVarArg, MF, TM, locs, C),
51 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs, LLVMContext &C, int NumNamedVarArgParams) argument
/freebsd-9.3-release/contrib/ntp/sntp/libopts/
H A DMakefile.in555 locs=`for p in $$list; do echo $$p; done | \
558 test -z "$$locs" || { \
559 echo rm -f $${locs}; \
560 rm -f $${locs}; \
566 locs=`for p in $$list; do echo $$p; done | \
569 test -z "$$locs" || { \
570 echo rm -f $${locs}; \
571 rm -f $${locs}; \
/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h222 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
/freebsd-9.3-release/contrib/llvm/include/llvm/TableGen/
H A DRecord.h1402 explicit Record(const std::string &N, ArrayRef<SMLoc> locs, argument
1404 ID(LastID++), Name(StringInit::get(N)), Locs(locs.begin(), locs.end()),
1408 explicit Record(Init *N, ArrayRef<SMLoc> locs, RecordKeeper &records, argument
1410 ID(LastID++), Name(N), Locs(locs.begin(), locs.end()),
/freebsd-9.3-release/contrib/ntp/sntp/libevent/
H A DMakefile.in1234 locs=`for p in $$list; do echo $$p; done | \
1237 test -z "$$locs" || { \
1238 echo rm -f $${locs}; \
1239 rm -f $${locs}; \
1245 locs=`for p in $$list; do echo $$p; done | \
1248 test -z "$$locs" || { \
1249 echo rm -f $${locs}; \
1250 rm -f $${locs}; \
/freebsd-9.3-release/contrib/binutils/gas/config/
H A Dtc-ia64.c1073 set_regstack (ins, locs, outs, rots)
1074 unsigned int ins, locs, outs, rots;
1079 sof = ins + locs + outs;
1092 md.out.base = md.loc.base + locs;
1095 md.loc.num_regs = locs;
4754 int ins, locs, outs, rots; local
4757 ins = locs = outs = rots = 0;
4763 locs = get_absolute_expression ();
4771 set_regstack (ins, locs, outs, rots);
/freebsd-9.3-release/contrib/llvm/tools/clang/lib/Sema/
H A DSemaLookup.cpp4091 IdentifierSourceLocations::iterator locs = TypoCorrectionFailures.find(Typo);
4092 if (locs != TypoCorrectionFailures.end() &&
4093 locs->second.count(TypoName.getLoc()))
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp78 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
80 : CCState(CC, isVarArg, MF, TM, locs, C) {
77 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs, LLVMContext &C, ParmContext PC) argument

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