/freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
H A D | SIFixSGPRCopies.cpp | 123 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 142 const TargetRegisterClass *RC = MRI.getRegClass(Reg); 169 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg); 183 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); 190 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg); 233 if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) 240 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
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H A D | SIInstrInfo.cpp | 197 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg()))) 399 return MRI.getRegClass(MI.getOperand(OpNo).getReg()); 402 return RI.getRegClass(RCID); 420 const TargetRegisterClass *RC = RI.getRegClass(RCID); 453 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) { 459 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { 467 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) { 488 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) 519 MRI.getRegClass(MI->getOperand(i).getReg());
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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H A D | RegAllocBase.cpp | 104 << MRI->getRegClass(VirtReg->reg)->getName() 124 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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H A D | VirtRegMap.cpp | 103 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); 124 << MRI->getRegClass(Reg)->getName() << "\n"; 132 << "] " << MRI->getRegClass(Reg)->getName() << "\n";
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H A D | TargetRegisterInfo.cpp | 97 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); 166 return TRI->getRegClass(I + countTrailingZeros(Common));
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H A D | PeepholeOptimizer.cpp | 174 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 185 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; 279 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); 445 const TargetRegisterClass *DefRC = MRI->getRegClass(Def); 467 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
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H A D | LiveRangeEdit.cpp | 34 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 43 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 416 << MRI.getRegClass(LI.reg)->getName() << '\n');
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H A D | CalcSpillWeights.cpp | 64 const TargetRegisterClass *rc = mri.getRegClass(reg);
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H A D | OptimizePHIs.cpp | 168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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H A D | Spiller.cpp | 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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H A D | TargetInstrInfo.cpp | 40 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, function in class:TargetInstrInfo 55 return TRI->getRegClass(RegClass); 357 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 362 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
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H A D | MachineSink.cpp | 135 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 136 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); 523 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
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H A D | MachineRegisterInfo.cpp | 55 const TargetRegisterClass *OldRC = getRegClass(Reg); 71 const TargetRegisterClass *OldRC = getRegClass(Reg);
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H A D | RegisterCoalescer.cpp | 284 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); 287 } else if (!MRI.getRegClass(Src)->contains(Dst)) { 292 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 293 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 649 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) 772 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); 822 RCForInst = TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), DefRC, 2238 << MRI->getRegClass(Reg)->getName() << '\n');
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H A D | TailDuplication.cpp | 285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { 394 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 431 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 441 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
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H A D | UnreachableBlockElim.cpp | 197 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
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H A D | InlineSpiller.cpp | 728 MRI.getRegClass(SVI.SpillReg), &TRI); 1160 MRI.getRegClass(NewVReg), &TRI); 1176 MRI.getRegClass(NewVReg), &TRI); 1291 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); 1342 << MRI.getRegClass(edit.getReg())->getName()
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 283 MRI->getRegClass(MI->getOperand(1).getReg()); 284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 544 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || 545 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { 561 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { 567 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && 671 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 162 DstRC = MRI->getRegClass(VRBase); 222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 253 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 334 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 441 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 500 TRC == MRI->getRegClass(SrcReg)) { 551 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 592 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 609 const TargetRegisterClass *RC = TRI->getRegClass(DstRCId [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); 39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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/freebsd-9.3-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenTarget.h | 125 return *getRegBank().getRegClass(R);
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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 300 /// constrainRegClass(ToReg, getRegClass(FromReg)) 340 /// getRegClass - Return the register class of the specified virtual register. 342 const TargetRegisterClass *getRegClass(unsigned Reg) const { function in class:llvm::MachineRegisterInfo 670 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
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/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 249 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 448 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 484 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 517 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || 518 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { 520 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
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