/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 154 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 738 MVT SrcVT = SrcEVT.getSimpleVT(); 750 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || 751 SrcVT == MVT::i8 || SrcVT == MVT::i1) { 761 switch (SrcVT.SimpleTy) { 801 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) 807 if (!PPCEmitIntExt(SrcVT, SrcReg 826 EVT SrcVT = TLI.getValueType(Src->getType(), true); local 844 EVT SrcVT = TLI.getValueType(Src->getType(), true); local 870 PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, bool IsSigned) argument 1021 MVT DstVT, SrcVT; local 1602 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument 1673 EVT SrcVT = TLI.getValueType(Src->getType(), true); local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 253 EVT SrcVT = Src.getValueType(); local 258 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 259 DAG.getConstant(Offset, SrcVT)),
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H A D | X86FastISel.cpp | 88 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 336 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 339 unsigned Src, EVT SrcVT, 341 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 837 EVT SrcVT = TLI.getValueType(RV->getType()); local 840 if (SrcVT != DstVT) { 841 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) 849 if (SrcVT 338 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 1561 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local 2347 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local [all...] |
H A D | X86ISelLowering.h | 775 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
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H A D | X86ISelLowering.cpp | 4876 MVT SrcVT = SV->getSimpleValueType(0); local 4881 int NumElems = SrcVT.getVectorNumElements(); 4882 bool Is256BitVec = SrcVT.is256BitVector(); 4884 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) && 4899 MVT EltVT = SrcVT.getVectorElementType(); 4907 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 5060 EVT SrcVT = V.getValueType(); local 5063 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 8479 EVT SrcVT local 8508 BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const argument 9264 MVT SrcVT = Op1.getSimpleValueType(); local 13259 MVT SrcVT = Op.getOperand(0).getSimpleValueType(); local [all...] |
H A D | X86ISelDAGToDAG.cpp | 495 MVT SrcVT = N->getOperand(0).getSimpleValueType(); local 499 if (SrcVT.isVector() || DstVT.isVector()) 506 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT); 527 MemVT = SrcIsSSE ? SrcVT : DstVT;
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 195 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 1454 MVT SrcVT = SrcEVT.getSimpleVT(); 1468 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || 1469 SrcVT == MVT::i1) { 1483 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) 1491 switch (SrcVT.SimpleTy) { 1533 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg 2650 EVT SrcVT, DestVT; local 2668 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument [all...] |
H A D | ARMISelLowering.cpp | 3721 EVT SrcVT = Tmp1.getValueType(); local 3738 if (SrcVT == MVT::f32) { 3772 if (SrcVT == MVT::f64) 3847 EVT SrcVT = Op.getValueType(); local 3849 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3853 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3863 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 385 EVT SrcVT = LD->getMemoryVT(); local 390 unsigned NumElem = SrcVT.getVectorNumElements(); 392 EVT SrcEltVT = SrcVT.getScalarType(); 395 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) { 411 unsigned RemainingBytes = SrcVT.getStoreSize(); 497 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; 503 SrcVT.getScalarType(),
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H A D | FastISel.cpp | 732 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local 735 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 745 if (!TLI.isTypeLegal(SrcVT)) 755 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 784 MVT SrcVT = SrcEVT.getSimpleVT(); 795 if (SrcVT == DstVT) { 796 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 808 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1068 EVT SrcVT local [all...] |
H A D | LegalizeFloatTypes.cpp | 1183 EVT SrcVT = Src.getValueType(); local 1190 if (SrcVT.bitsLE(MVT::i32)) { 1199 if (SrcVT.bitsLE(MVT::i64)) { 1203 } else if (SrcVT.bitsLE(MVT::i128)) { 1218 SrcVT = Src.getValueType(); 1226 switch (SrcVT.getSimpleVT().SimpleTy) { 1244 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, SrcVT),
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H A D | LegalizeDAG.cpp | 932 EVT SrcVT = LD->getMemoryVT(); 933 unsigned SrcWidth = SrcVT.getSizeInBits(); 939 if (SrcWidth != SrcVT.getStoreSizeInBits() && 947 (SrcVT != MVT::i1 || 951 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 956 // way. A zext load from NVT thus automatically gives zext from SrcVT. 972 Result, DAG.getValueType(SrcVT)); 977 DAG.getValueType(SrcVT)); 983 assert(!SrcVT.isVector() && "Unsupported extload!"); 1059 switch (TLI.getLoadExtAction(ExtType, SrcVT [all...] |
H A D | LegalizeVectorTypes.cpp | 912 EVT SrcVT = N->getOperand(0).getValueType(); local 930 unsigned NumElements = SrcVT.getVectorNumElements(); 932 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { 936 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2), 939 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2); 942 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
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H A D | LegalizeIntegerTypes.cpp | 2796 EVT SrcVT = Op.getValueType(); local 2800 // The following optimization is valid only if every value in SrcVT (when 2802 // size of DstVT is >= than the number of bits in SrcVT -1. 2804 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 && 2805 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2819 if (SrcVT == MVT::i32) 2821 else if (SrcVT == MVT::i64) 2823 else if (SrcVT == MVT::i128) 2863 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
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H A D | SelectionDAGISel.cpp | 619 EVT SrcVT = Src.getValueType(); local 620 if (!SrcVT.isInteger() || SrcVT.isVector())
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H A D | DAGCombiner.cpp | 9613 EVT SrcVT = MVT::Other; local 9637 if (SrcVT == MVT::Other) 9638 SrcVT = InVT; 9639 if (SrcVT != InVT) 9651 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 9653 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 9663 Opnds.push_back(DAG.getUNDEF(SrcVT));
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H A D | SelectionDAGBuilder.cpp | 3008 EVT SrcVT = Src1.getValueType(); 3009 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 3045 SDValue UndefVal = DAG.getUNDEF(SrcVT);
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/freebsd-9.3-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | CodeGenPrepare.cpp | 456 EVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); local 460 if (SrcVT.isInteger() != DstVT.isInteger()) 465 if (SrcVT.bitsLT(DstVT)) return false; 470 if (TLI.getTypeAction(CI->getContext(), SrcVT) == 472 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT); 478 if (SrcVT != DstVT)
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