| /freebsd-9.3-release/contrib/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
53 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, argument
64 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, argument
75 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, argument
86 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, argument
97 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, argument
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
119 assert(Src1
136 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
150 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
164 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...] |
| /freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
| H A D | R600ExpandSpecialInstrs.cpp | 215 unsigned Src1 = BMI->getOperand( local
219 (void) Src1;
221 (TRI.getEncodingValue(Src1) & 0xff) < 127)
222 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
266 unsigned Src1 = 0; local
272 Src1 = MI.getOperand(Src1Idx).getReg();
278 Src1 = TRI.getSubReg(Src1, SubRegIndex);
283 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
318 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
[all...] |
| H A D | SIInstrInfo.cpp | 345 const MachineOperand &Src1 = MI->getOperand(Src1Idx); local
346 if (Src1.isImm() || Src1.isFPImm()) {
447 MachineOperand &Src1 = MI->getOperand(Src1Idx); local
458 if (ReadsVCC && Src1.isReg() &&
459 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
466 if (Src1.isImm() || Src1.isFPImm() ||
467 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1
[all...] |
| H A D | R600InstrInfo.cpp | 1231 MachineOperand &Src1 = MI->getOperand(
1234 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
|
| /freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 157 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
160 SDValue Src1, SDValue Src2, uint64_t Size) {
162 EVT PtrVT = Src1.getValueType();
172 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
175 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
194 SDValue Src1, SDValue Src2, SDValue Size,
200 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes);
250 SDValue Src1, SDValue Src2,
253 SDVTList VTs = DAG.getVTList(Src1
159 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument
193 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
249 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
[all...] |
| H A D | SystemZSelectionDAGInfo.h | 45 SDValue Src1, SDValue Src2, SDValue Size,
63 SDValue Src1, SDValue Src2,
|
| /freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 159 MachineOperand &Src1 = MI->getOperand(1); local
161 if (Src1.getImm() != 0)
176 MachineOperand &Src1 = MI->getOperand(1); local
181 unsigned SrcReg = Src1.getReg();
|
| H A D | HexagonISelDAGToDAG.cpp | 1328 SDNode* Src1 = N->getOperand(0).getNode(); local
1329 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1330 || Src1->getValueType(0) != MVT::i32) {
1338 Src1->getOperand(0),
1339 Src1->getOperand(1));
|
| /freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 2999 SDValue Src1 = getValue(I.getOperand(0));
3008 EVT SrcVT = Src1.getValueType();
3012 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3023 // First check for Src1 in low and Src2 in high
3028 VT, Src1, Src2));
3031 // Then check for Src2 in low and Src1 in high
3036 VT, Src2, Src1));
3043 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3049 MOps1[0] = Src1;
3052 Src1
[all...] |
| H A D | LegalizeVectorTypes.cpp | 1152 SDValue Src1 = N->getOperand(2); local
1168 llvm::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
|
| /freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2683 SDValue Src1 = Op.getOperand(0); local
2684 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2685 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
|
| /freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6709 unsigned Src1 = MI->getOperand(1).getReg(); local
6724 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
|