/freebsd-9.3-release/contrib/llvm/tools/clang/include/clang/Basic/ |
H A D | OperatorPrecedence.h | 39 Shift = 11, // <<, >> enumerator in enum:clang::prec::Level
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/freebsd-9.3-release/contrib/llvm/include/llvm/Support/ |
H A D | LEB128.h | 83 unsigned Shift = 0; local 85 Value += (*p & 0x7f) << Shift; 86 Shift += 7;
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H A D | MathExtras.h | 59 T Shift = std::numeric_limits<T>::digits >> 1; local 60 T Mask = std::numeric_limits<T>::max() >> Shift; 61 while (Shift) { 63 Val >>= Shift; local 64 ZeroBits |= Shift; 66 Shift >>= 1; 67 Mask >>= Shift; local 128 for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >> [all...] |
/freebsd-9.3-release/contrib/llvm/tools/clang/lib/Basic/ |
H A D | OperatorPrecedence.cpp | 38 return prec::Shift; 65 case tok::lessless: return prec::Shift;
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/freebsd-9.3-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombinePHI.cpp | 558 unsigned Shift; // The amount shifted. member in struct:__anon2596::PHIUsageRecord 562 : PHIId(pn), Shift(Sh), Inst(User) {} 567 if (Shift < RHS.Shift) return true; 568 if (Shift > RHS.Shift) return false; 576 unsigned Shift; // The amount shifted. member in struct:__anon2596::LoweredPHIRecord 580 : PN(pn), Shift(Sh), Width(Ty->getPrimitiveSizeInBits()) {} 584 : PN(pn), Shift(Sh), Width(0) {} 598 return DenseMapInfo<PHINode*>::getHashValue(Val.PN) ^ (Val.Shift>> 676 unsigned Shift = cast<ConstantInt>(User->getOperand(1))->getZExtValue(); local [all...] |
H A D | InstCombineCasts.cpp | 490 Value *Shift = Builder->CreateLShr(A, Cst->getZExtValue()); 491 Shift->takeName(Src); 492 return CastInst::CreateIntegerCast(Shift, CI.getType(), false); 617 // Shift the bit we're testing down to the lsb. 1526 /// Shift is the number of bits between the lsb of V and the lsb of 1531 static bool CollectInsertionElements(Value *V, unsigned Shift, argument 1534 assert(isMultipleOfTypeSize(Shift, VecEltTy) && 1535 "Shift should be a multiple of the element type size"); 1548 unsigned ElementIndex = getTypeSizeIndex(Shift, VecEltTy); 1569 Shift, Element [all...] |
H A D | InstCombineCompares.cpp | 1191 BinaryOperator *Shift = dyn_cast<BinaryOperator>(LHSI->getOperand(0)); local 1192 if (Shift && !Shift->isShift()) 1193 Shift = 0; 1196 ShAmt = Shift ? dyn_cast<ConstantInt>(Shift->getOperand(1)) : 0; 1197 Type *Ty = Shift ? Shift->getType() : 0; // Type of the shift. 1209 unsigned ShiftOpcode = Shift->getOpcode(); 1227 if (Shift [all...] |
H A D | InstCombineShifts.cpp | 604 Value *Shift = Builder->CreateLShr(X, ShiftDiffCst); local 607 return BinaryOperator::CreateAnd(Shift, 652 Value *Shift = Builder->CreateShl(X, ShiftDiffCst); 655 return BinaryOperator::CreateAnd(Shift,
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 96 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 364 unsigned Shift = 32; local 368 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) 373 if (isShiftMask) Mask = Mask << Shift; 375 Indeterminant = ~(0xFFFFFFFFu << Shift); 378 if (isShiftMask) Mask = Mask >> Shift; 380 Indeterminant = ~(0xFFFFFFFFu >> Shift); 382 Shift = 32 - Shift; 894 unsigned Shift = 0; local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 67 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; local 68 EmitByte((Val >> Shift) & 0xff, OS); 153 int64_t Shift = Inst.getOperand(2).getImm(); local 154 if (Shift <= 31) 156 Shift -= 32; 159 Inst.getOperand(2).setImm(Shift);
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/freebsd-9.3-release/contrib/llvm/include/llvm/Analysis/ |
H A D | BlockFrequencyImpl.h | 250 unsigned Shift = 32 - countLeadingZeros(D); local 251 D >>= Shift; local 252 N >>= Shift; local
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 131 template<A64SE::ShiftExtSpecifiers Shift> 133 printShiftOperand(MI, OpNum, O, Shift);
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H A D | AArch64InstPrinter.cpp | 258 A64SE::ShiftExtSpecifiers Shift) { 262 if (Shift == A64SE::LSL && MO.isImm() && MO.getImm() == 0) 265 switch (Shift) { 256 printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, A64SE::ShiftExtSpecifiers Shift) argument
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/freebsd-9.3-release/sys/boot/pc98/boot0.5/ |
H A D | putssjis.s | 35 # Display string with Shift-JIS support 113 # Convert Shift-JIS into JIS.
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/freebsd-9.3-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | ScalarReplAggregates.cpp | 2357 uint64_t Shift = Layout->getElementOffsetInBits(i); local 2360 Shift = AllocaSizeBits-Shift-TD->getTypeAllocSizeInBits(FieldTy); 2363 if (Shift) { 2364 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); 2397 uint64_t Shift; local 2400 Shift = AllocaSizeBits-ElementOffset; 2402 Shift = 0; 2409 if (Shift) { 2410 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); 2501 uint64_t Shift; local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 1070 bool A64Imms::isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { argument 1079 Shift = i / 16; 1087 bool A64Imms::isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { argument 1098 return isMOVZImm(RegWidth, MOVZEquivalent, UImm16, Shift); 1102 int &UImm16, int &Shift) { 1103 if (isMOVZImm(RegWidth, Value, UImm16, Shift)) 1106 return isMOVNImm(RegWidth, Value, UImm16, Shift); 1101 isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) argument
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H A D | AArch64BaseInfo.h | 1124 bool isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift); 1125 bool isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift); 1129 bool isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
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/freebsd-9.3-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 775 SDValue Shift, SDValue X, 777 if (Shift.getOpcode() != ISD::SRL || 778 !isa<ConstantSDNode>(Shift.getOperand(1)) || 779 !Shift.hasOneUse()) 782 int ScaleLog = 8 - Shift.getConstantOperandVal(1); 818 SDValue Shift, SDValue X, 820 if (Shift.getOpcode() != ISD::SHL || 821 !isa<ConstantSDNode>(Shift.getOperand(1))) 827 if (!N.hasOneUse() || !Shift.hasOneUse()) 831 unsigned ShiftAmt = Shift 773 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 816 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 883 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 1242 SDValue Shift = N.getOperand(0); local [all...] |
/freebsd-9.3-release/contrib/compiler-rt/lib/sparc64/ |
H A D | divmod.m4 | 144 ! Compute ITER in an unorthodox manner: know we need to Shift V into
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/freebsd-9.3-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 538 uint32_t Shift = 2 * (VT.SimpleTy & 0xF); 540 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3); 1042 uint32_t Shift = 2 * (VT.SimpleTy & 0xF); 1043 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift); 1044 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
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/freebsd-9.3-release/contrib/llvm/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 839 unsigned Shift = 0; 842 Value += (*I & 0x7f) << Shift; 843 Shift += 7; 849 Shift = 0; 852 Value += (*I & 0x7f) << Shift; 853 Shift += 7;
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 349 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 3287 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { argument 3298 Shift = Op; 3753 SDValue Shift; local 3756 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0), 3760 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), 3763 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift, 3867 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT, local 3870 Shift); 4318 SDValue Shift local 7607 unsigned Shift; member in struct:__anon2178::LoadedSlice::Cost 7684 unsigned Shift; member in struct:__anon2178::LoadedSlice 7712 UsedBits <<= Shift; local 8062 unsigned Shift = 0; local 10552 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), local 10564 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), local 10716 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType, local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/ |
H A D | ScheduleDAG.cpp | 458 /// the nodes reachable from Y, and then shifts them using Shift to lie 531 Shift(Visited, LowerBound, UpperBound); 544 /// topological indexes by means of the Shift method. 572 /// Shift - Renumber the nodes so that the topological ordering is 574 void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 434 int UImm16, Shift; local 435 return !A64Imms::isMOVZImm(RegWidth, CE->getValue(), UImm16, Shift) 436 && !A64Imms::isMOVNImm(RegWidth, CE->getValue(), UImm16, Shift); 606 int UImm16, Shift; local 619 return isValidImm(RegWidth, Value, UImm16, Shift); 1128 int UImm16, Shift; local 1137 bool Valid = isValidImm(RegWidth, Value, UImm16, Shift); 1142 Inst.addOperand(MCOperand::CreateImm(Shift));
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/freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDILISelLowering.cpp | 343 SDValue Shift = DAG.getConstant(shiftBits, DVT); local 344 // Shift left by 'Shift' bits. 345 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift); 346 // Signed shift Right by 'Shift' bits. 347 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
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