Searched refs:SVOp (Results 1 - 4 of 4) sorted by relevance

/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3861 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, argument
3863 MVT VT = SVOp->getSimpleValueType(0);
3864 SDLoc dl(SVOp);
3869 ArrayRef<int> Mask = SVOp->getMask();
3888 SDValue Op0 = SVOp->getOperand(0);
3889 SDValue Op1 = SVOp->getOperand(1);
4134 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { argument
4135 MVT VT = SVOp->getSimpleValueType(0);
4141 if (SVOp->getMaskElt(i) > 0) {
4142 FstHalf = SVOp
4473 getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) argument
4566 CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
5081 getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, bool ZerosFromLeft, SelectionDAG &DAG, unsigned PreferredNum = -1U) argument
5107 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum) argument
5135 isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument
5170 isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument
5205 isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument
5535 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); local
6173 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
6239 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); local
6354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); local
6428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); local
6452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); local
6491 LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, const X86Subtarget* Subtarget, SelectionDAG &DAG) argument
6620 LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
6669 RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
6744 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
6858 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
7205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); local
7262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); local
16126 isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) argument
16142 isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) argument
16160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); local
802 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
809 unsigned ShiftAmt = SVOp->getMaskElt(i);
816 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
821 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
876 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); local
877 assert(isSplatShuffleMask(SVOp, EltSize));
878 return SVOp->getMaskElt(0) / EltSize;
5462 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); local
5469 if (PPC::isSplatShuffleMask(SVOp,
[all...]
/freebsd-9.3-release/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGExprScalar.cpp1183 Value *SVOp = SVI->getOperand(0); local
1184 llvm::VectorType *OpTy = cast<llvm::VectorType>(SVOp->getType());
1204 Init = SVOp;
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp9317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); local
9319 int OrigElt = SVOp->getMaskElt(Elt);

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