| /freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2047 EVT ResVT = N->getValueType(0); local
2050 assert(ResVT.isVector() && "Vector load must have vector type");
2055 assert(ResVT.isSimple() && "Can only handle simple types");
2056 switch (ResVT.getSimpleVT().SimpleTy) {
2073 EVT EltVT = ResVT.getVectorElementType();
2074 unsigned NumElts = ResVT.getVectorNumElements();
2124 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
2131 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, &ScalarRes[0], NumElts);
2154 EVT ResVT = N->getValueType(0); local
2156 if (ResVT
[all...] |
| /freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1181 EVT ResVT = N->getValueType(0); local
1187 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1193 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1413 EVT ResVT = N->getValueType(0); local
1419 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1425 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2459 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), local
2463 ResVT, WideSETCC, DAG.getConstant(0,
|
| H A D | LegalizeIntegerTypes.cpp | 168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); local
170 N->getMemoryVT(), ResVT,
|
| H A D | DAGCombiner.cpp | 7855 EVT ResVT = Use->getValueType(0); local
7856 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
7859 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
7873 ResVT.getTypeForEVT(*DAG->getContext()));
7879 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
|
| /freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1009 EVT ResVT = N->getValueType(0); local
1010 bool is64BitRes = ResVT.is64BitVector();
1023 return CurDAG->getMachineNode(Opc, dl, ResVT, Ops);
|
| /freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4712 EVT ResVT = Op.getValueType(); local
4729 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4732 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4741 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4749 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4762 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4765 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4772 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4778 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4784 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cm
[all...] |
| /freebsd-9.3-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2286 EVT ResVT = RVLocs[i].getValVT(); local
2287 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
2288 unsigned MemSize = ResVT.getSizeInBits()/8;
2293 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
|
| H A D | X86ISelLowering.cpp | 6149 MVT ResVT = Op.getSimpleValueType(); local
6151 assert((ResVT.is256BitVector() ||
6152 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6156 unsigned NumElems = ResVT.getVectorNumElements();
6157 if(ResVT.is256BitVector())
6158 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6160 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7893 MVT ResVT = Op.getSimpleValueType(); local
7897 if (ResVT.is128BitVector() &&
7902 if (ResVT
[all...] |
| /freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1679 EVT ResVT = Op.getValueType(); local
1681 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1697 if (InVT == MVT::f32 && ResVT == MVT::i32) {
|