Searched refs:Reg (Results 1 - 25 of 266) sorted by relevance

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/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
48 VRegInfo[Reg].first = RC;
52 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
55 const TargetRegisterClass *OldRC = getRegClass(Reg);
64 setRegClass(Reg, NewRC);
69 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument
71 const TargetRegisterClass *OldRC = getRegClass(Reg);
80 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
96 setRegClass(Reg, NewRC);
110 unsigned Reg local
123 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DLiveRegUnits.cpp54 unsigned Reg = O->getReg(); local
55 if (Reg == 0)
57 removeReg(Reg, MCRI);
66 unsigned Reg = O->getReg(); local
67 if (Reg == 0)
69 addReg(Reg, MCRI);
82 unsigned Reg = O->getReg(); local
83 if (Reg == 0)
87 Defs.push_back(Reg);
92 removeReg(Reg, MCR
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H A DMachineInstrBundle.cpp133 unsigned Reg = MO.getReg(); local
134 if (!Reg)
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if (LocalDefSet.count(Reg)) {
141 KilledDefSet.insert(Reg);
143 if (ExternUseSet.insert(Reg)) {
144 ExternUses.push_back(Reg);
146 UndefUseSet.insert(Reg);
150 KilledUseSet.insert(Reg);
156 unsigned Reg local
187 unsigned Reg = LocalDefs[i]; local
197 unsigned Reg = ExternUses[i]; local
252 analyzeVirtReg(unsigned Reg, SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) argument
281 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument
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H A DAggressiveAntiDepBreaker.cpp60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
106 IsLive(unsigned Reg) argument
160 unsigned Reg = *AI; local
173 unsigned Reg = *I; local
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H A DCriticalAntiDepBreaker.cpp66 unsigned Reg = *AI; local
67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
68 KillIndices[Reg] = BBSize;
69 DefIndices[Reg] = ~0u;
81 unsigned Reg = *AI; local
82 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
83 KillIndices[Reg] = BBSize;
84 DefIndices[Reg] = ~0u;
100 for (unsigned Reg = 0; Reg !
172 unsigned Reg = MO.getReg(); local
235 unsigned Reg = MO.getReg(); local
266 unsigned Reg = MO.getReg(); local
579 unsigned Reg = MO.getReg(); local
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H A DDeadMachineInstructionElim.cpp69 unsigned Reg = MO.getReg(); local
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
75 if (!MRI->use_nodbg_empty(Reg))
127 unsigned Reg = MO.getReg(); local
128 if (!TargetRegisterInfo::isVirtualRegister(Reg))
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
155 unsigned Reg = MO.getReg(); local
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
174 unsigned Reg = MO.getReg(); local
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H A DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument
183 VarInfo &VRInfo = getVarInfo(Reg);
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg)) {
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument
232 MachineInstr *LastDef = PhysRegDef[Reg];
234 if (!LastDef && !PhysRegUse[Reg]) {
242 // All of the sub-registers must have been defined before the use of Reg!
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg
281 FindLastRefOrPartRef(unsigned Reg) argument
311 HandlePhysRegKill(unsigned Reg, MachineInstr *MI) argument
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) argument
489 unsigned Reg = Defs.back(); local
651 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
676 replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI) argument
689 unsigned Reg = MO.getReg(); local
714 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument
732 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument
813 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DAllocationOrder.h52 unsigned Reg = Order[Pos++]; local
53 if (!isHint(Reg))
54 return Reg;
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.h73 bool isAllocated(unsigned Reg) const {
74 return UsedRegs[Reg/32] & (1 << (Reg&31));
120 unsigned AllocateReg(unsigned Reg) { argument
121 if (isAllocated(Reg)) return 0;
122 MarkAllocated(Reg);
123 return Reg;
127 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
128 if (isAllocated(Reg)) return 0;
129 MarkAllocated(Reg);
143 unsigned Reg = Regs[FirstUnalloc]; local
156 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h54 unsigned getFirstReg(unsigned Reg);
57 inline unsigned getRegAsGR64(unsigned Reg) { argument
58 return GR64Regs[getFirstReg(Reg)];
62 inline unsigned getRegAsGR32(unsigned Reg) { argument
63 return GR32Regs[getFirstReg(Reg)];
67 inline unsigned getRegAsGRH32(unsigned Reg) { argument
68 return GRH32Regs[getFirstReg(Reg)];
/freebsd-9.3-release/sys/contrib/dev/acpica/hardware/
H A Dhwregs.c75 * PARAMETERS: Reg - GAS register structure
89 ACPI_GENERIC_ADDRESS *Reg,
96 if (!Reg)
106 ACPI_MOVE_64_TO_64 (Address, &Reg->Address);
114 if ((Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
115 (Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_IO))
118 "Unsupported address space: 0x%X", Reg->SpaceId));
124 if ((Reg->BitWidth != 8) &&
125 (Reg->BitWidth != 16) &&
126 (Reg
88 AcpiHwValidateRegister( ACPI_GENERIC_ADDRESS *Reg, UINT8 MaxBitWidth, UINT64 *Address) argument
168 AcpiHwRead( UINT32 *Value, ACPI_GENERIC_ADDRESS *Reg) argument
231 AcpiHwWrite( UINT32 Value, ACPI_GENERIC_ADDRESS *Reg) argument
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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DLiveVariables.h106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
110 unsigned Reg,
150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
281 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
299 isPHIJoin(unsigned Reg) argument
302 setPHIJoin(unsigned Reg) argument
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H A DLiveRegUnits.h50 void addReg(unsigned Reg, const MCRegisterInfo &MCRI) { argument
51 for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
56 void removeReg(unsigned Reg, const MCRegisterInfo &MCRI) { argument
57 for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
64 /// \brief Returns true if register @p Reg (or one of its super register) is
66 bool contains(unsigned Reg, const MCRegisterInfo &MCRI) const { argument
67 for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) {
H A DRegisterScavenging.h45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {}
52 unsigned Reg; member in struct:llvm::RegScavenger::ScavengedInfo
162 void setUsed(unsigned Reg);
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
171 bool isUsed(unsigned Reg, bool CheckReserved = true) const { argument
172 return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
175 /// isAliasUsed - Is Reg or an alias currently in use?
176 bool isAliasUsed(unsigned Reg) cons
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H A DMachineRegisterInfo.h35 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
90 return MO->Contents.Reg.Next;
194 /// Verify the sanity of the use list for Reg.
195 void verifyUseList(unsigned Reg) const;
230 /// Reg are Debug instructions.
309 MachineInstr *getVRegDef(unsigned Reg) const;
314 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
320 void clearKillFlags(unsigned Reg) const;
342 const TargetRegisterClass *getRegClass(unsigned Reg) const {
343 return VRegInfo[Reg]
385 setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) argument
434 setPhysRegUsed(unsigned Reg) argument
448 setPhysRegUnused(unsigned Reg) argument
521 addLiveIn(unsigned Reg, unsigned vreg = 0) argument
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H A DLiveIntervalAnalysis.h105 LiveInterval &getInterval(unsigned Reg) { argument
106 if (hasInterval(Reg))
107 return *VirtRegIntervals[Reg];
109 return createAndComputeVirtRegInterval(Reg);
112 const LiveInterval &getInterval(unsigned Reg) const {
113 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
116 bool hasInterval(unsigned Reg) const {
117 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
121 LiveInterval &createEmptyInterval(unsigned Reg) { argument
128 createAndComputeVirtRegInterval(unsigned Reg) argument
135 removeInterval(unsigned Reg) argument
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H A DCallingConvLower.h239 bool isAllocated(unsigned Reg) const {
240 return UsedRegs[Reg/32] & (1 << (Reg&31));
291 unsigned AllocateReg(unsigned Reg) { argument
292 if (isAllocated(Reg)) return 0;
293 MarkAllocated(Reg);
294 return Reg;
298 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
299 if (isAllocated(Reg)) return 0;
300 MarkAllocated(Reg);
314 unsigned Reg = Regs[FirstUnalloc]; local
327 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h35 void setLowSavedGPR(unsigned Reg) { LowSavedGPR = Reg; } argument
40 void setHighSavedGPR(unsigned Reg) { HighSavedGPR = Reg; } argument
H A DSystemZShortenInst.cpp78 unsigned Reg = MI.getOperand(0).getReg(); local
79 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
80 unsigned GPRs = GPRMap[Reg];
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
111 unsigned Reg = *LI;
112 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
113 LiveLow |= LowGPRs[Reg];
114 LiveHigh |= HighGPRs[Reg];
135 if (unsigned Reg
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/freebsd-9.3-release/contrib/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp88 unsigned Reg,
92 unsigned Reg,
129 /// This functions walks the use list of Reg until it finds an Instruction
135 unsigned Reg,
137 // The Reg parameter to the function must always be defined by either a PHI
139 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
140 "Reg cannot be a physical register");
142 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
144 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
161 unsigned Reg,
132 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
158 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
221 unsigned Reg = MI.getOperand(i).getReg(); local
226 unsigned Reg = MI.getOperand(0).getReg(); local
239 unsigned Reg = MI.getOperand(i).getReg(); local
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H A DR600RegisterInfo.h42 virtual unsigned getHWRegIndex(unsigned Reg) const;
50 // \returns true if \p Reg can be defined in one ALU caluse and used in another.
51 virtual bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
H A DSIRegisterInfo.h45 virtual unsigned getHWRegIndex(unsigned Reg) const;
49 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 unsigned Reg = MI->getOperand(1).getReg(); local
90 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 MachineInstr *DefMI = MRI->getVRegDef(Reg);
99 Reg = DefMI->getOperand(1).getReg();
100 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
101 DefMI = MRI->getVRegDef(Reg);
105 Reg = DefMI->getOperand(2).getReg();
106 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
107 DefMI = MRI->getVRegDef(Reg);
117 unsigned Reg = MI->getOperand(0).getReg(); local
143 unsigned Reg = MI->getOperand(1).getReg(); local
184 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument
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