Searched refs:RADEON_READ (Results 1 - 10 of 10) sorted by relevance

/freebsd-9.3-release/sys/dev/drm/
H A Dradeon_irq.c137 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
148 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
229 tmp = RADEON_READ(RADEON_AIC_CNTL) &
238 tmp = RADEON_READ(RADEON_BUS_CNTL) &
245 tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
280 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
286 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
310 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
312 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
315 return RADEON_READ(RADEON_CRTC_CRNT_FRAM
[all...]
H A Dradeon_cp.c69 return RADEON_READ(R600_CP_RB_RPTR);
71 return RADEON_READ(RADEON_CP_RB_RPTR);
100 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
102 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
124 ret = RADEON_READ(R520_MC_IND_DATA);
133 ret = RADEON_READ(RS480_NB_MC_DATA);
142 ret = RADEON_READ(RS690_MC_DATA);
152 ret = RADEON_READ(RS600_MC_DATA);
171 return RADEON_READ(R700_MC_VM_FB_LOCATION);
173 return RADEON_READ(R600_MC_VM_FB_LOCATIO
[all...]
H A Dr600_cp.c80 slots = (RADEON_READ(R600_GRBM_STATUS)
83 slots = (RADEON_READ(R600_GRBM_STATUS)
90 RADEON_READ(R600_GRBM_STATUS),
91 RADEON_READ(R600_GRBM_STATUS2));
109 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
114 RADEON_READ(R600_GRBM_STATUS),
115 RADEON_READ(R600_GRBM_STATUS2));
211 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
338 RADEON_READ(R600_GRBM_SOFT_RESET);
447 RADEON_READ(R600_GRBM_SOFT_RESE
[all...]
H A Dradeon_state.c2155 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2158 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
H A Dradeon_drv.h1825 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) macro
/freebsd-9.3-release/sys/dev/drm2/radeon/
H A Dradeon_irq.c136 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
147 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
248 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
254 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
275 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
277 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
280 return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
282 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
H A Dradeon_cp.c80 return RADEON_READ(R600_CP_RB_RPTR);
82 return RADEON_READ(RADEON_CP_RB_RPTR);
111 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
113 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
121 ret = RADEON_READ(R520_MC_IND_DATA);
130 ret = RADEON_READ(RS480_NB_MC_DATA);
139 ret = RADEON_READ(RS690_MC_DATA);
149 ret = RADEON_READ(RS600_MC_DATA);
168 return RADEON_READ(R700_MC_VM_FB_LOCATION);
170 return RADEON_READ(R600_MC_VM_FB_LOCATIO
[all...]
H A Dr600_cp.c88 slots = (RADEON_READ(R600_GRBM_STATUS)
91 slots = (RADEON_READ(R600_GRBM_STATUS)
98 RADEON_READ(R600_GRBM_STATUS),
99 RADEON_READ(R600_GRBM_STATUS2));
117 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
122 RADEON_READ(R600_GRBM_STATUS),
123 RADEON_READ(R600_GRBM_STATUS2));
226 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
394 RADEON_READ(R600_GRBM_SOFT_RESET);
487 RADEON_READ(R600_GRBM_SOFT_RESE
[all...]
H A Dradeon_state.c2195 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2198 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
H A Dradeon_drv.h1845 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) macro

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