/freebsd-9.3-release/contrib/llvm/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); 49 assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
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H A D | AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===// 30 ArrayRef<MCPhysReg> Order; member in class:llvm::AllocationOrder 43 ArrayRef<MCPhysReg> getOrder() const { return Order; } 51 while (Pos < int(Order.size())) { 52 unsigned Reg = Order[Pos++]; 67 return Order[Pos++];
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H A D | RegisterClassInfo.cpp | 84 if (!RCI.Order) 85 RCI.Order.reset(new MCPhysReg[NumRegs]); 110 RCI.Order[N++] = PhysReg; 123 RCI.Order[N++] = PhysReg; 142 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
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H A D | TargetRegisterInfo.cpp | 133 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); local 134 for (unsigned i = 0; i != Order.size(); ++i) 135 R.set(Order[i]); 265 ArrayRef<MCPhysReg> Order, 290 if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) 264 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const argument
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H A D | RegAllocGreedy.cpp | 457 AllocationOrder &Order, 459 Order.rewind(); 461 while ((PhysReg = Order.next())) 464 if (!PhysReg || Order.isHint()) 472 if (Order.isHint(Hint)) { 490 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); 500 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 502 while ((PhysReg = Order.next())) { 679 /// @param Order Physregs to try. 682 AllocationOrder &Order, 456 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 681 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit) argument 1172 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1307 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1359 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1493 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument [all...] |
H A D | RegAllocBasic.cpp | 228 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 229 while (unsigned PhysReg = Order.next()) {
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H A D | AggressiveAntiDepBreaker.cpp | 602 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); 603 if (Order.empty()) { 611 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); 614 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR); 617 if (R == 0) R = Order.size(); 619 const unsigned NewSuperReg = Order[R];
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H A D | CriticalAntiDepBreaker.cpp | 366 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); local 367 for (unsigned i = 0; i != Order.size(); ++i) { 368 unsigned NewReg = Order[i];
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H A D | ScheduleDAG.cpp | 344 case SDep::Order: dbgs() << "ch "; break; 364 case SDep::Order: dbgs() << "ch "; break;
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SDNodeDbgValue.h | 50 unsigned Order; member in class:llvm::SDDbgValue 55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O), 65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { 72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { 103 unsigned getOrder() { return Order; }
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H A D | ScheduleDAGSDNodes.cpp | 702 DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) { 715 if (!Order || DVOrder == ++Order) { 734 unsigned Order = N->getIROrder(); 735 if (!Order || !Seen.insert(Order)) { 748 Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); 752 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos()))); 753 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); 866 unsigned Order [all...] |
H A D | SelectionDAGDumper.cpp | 498 if (unsigned Order = getIROrder()) 499 OS << " [ORD=" << Order << ']'; local
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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 34 OwningArrayPtr<MCPhysReg> Order; member in struct:llvm::RegisterClassInfo::RCInfo 41 return makeArrayRef(Order.get(), NumRegs);
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H A D | SelectionDAGNodes.h | 428 void setIROrder(unsigned Order) { IROrder = Order; } argument 701 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs, 708 debugLoc(dl), IROrder(Order) { 718 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs) 722 debugLoc(dl), IROrder(Order) {} 814 SDLoc(const Instruction *I, int Order) : Ptr(I), IROrder(Order) { 815 assert(Order >= 0 && "bad IROrder"); 906 UnarySDNode(unsigned Opc, unsigned Order, DebugLo argument 918 BinarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y) argument 930 TernarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y, SDValue Z) argument 1109 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 1118 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 1127 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 1136 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue* AllOps, SDUse *DynOps, unsigned NumOps, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument 1180 MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO) argument 1213 ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1, SDValue N2, const int *M) argument 1587 EHLabelSDNode(unsigned Order, DebugLoc dl, SDValue ch, MCSymbol *L) argument 1640 CvtRndSatSDNode(EVT VT, unsigned Order, DebugLoc dl, const SDValue *Ops, unsigned NumOps, ISD::CvtCode Code) argument 1684 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument 1722 LoadSDNode(SDValue *ChainPtrOff, unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument 1751 StoreSDNode(SDValue *ChainValuePtrOff, unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument 1787 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc DL, SDVTList VTs) argument [all...] |
H A D | ScheduleDAG.h | 52 Order ///< Any other ordering dependency. enumerator in enum:llvm::SDep::Kind 85 /// Order - Additional information about Order dependencies. 120 : Dep(S, Order), Contents(), Latency(0) { 132 case Order: 179 /// isNormalMemory - Test if this is an Order dependence between two 183 return getKind() == Order && (Contents.OrdKind == MayAliasMem 187 /// isMustAlias - Test if this is an Order dependence that is marked 191 return getKind() == Order && Contents.OrdKind == MustAliasMem; 199 return getKind() == Order [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | StructurizeCFG.cpp | 169 RNVector Order; member in class:__anon2691::StructurizeCFG 282 for (Order.clear(); I != E; ++I) { 284 Order.append(Nodes.begin(), Nodes.end()); 443 for (RNVector::reverse_iterator OI = Order.rbegin(), OE = Order.rend(); 645 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : 646 Order.back()->getEntry(); 677 if (Order.empty() && ExitUseAllowed) { 729 RegionNode *Node = Order.pop_back_val(); 753 while (!Order [all...] |
/freebsd-9.3-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 58 // Order CodeGenSubRegIndex pointers by EnumValue. 207 // Order CodeGenRegister pointers by EnumValue. 243 // Allocation orders. Order[0] always contains all registers in Members. 437 unsigned Order; // Cache the sort key. member in struct:llvm::RegUnitSet 439 RegUnitSet() : Weight(0), Order(0) {} 632 unsigned getRegSetIDAt(unsigned Order) const { 633 return RegUnitSetOrder[Order]; 635 const RegUnitSet &getRegSetAt(unsigned Order) const { 636 return RegUnitSets[RegUnitSetOrder[Order]];
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H A D | RegisterInfoEmitter.cpp | 259 PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order); 854 ArrayRef<Record*> Order = RC.getOrder(); local 863 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 864 Record *Reg = Order[i]; 873 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 874 Record *Reg = Order[i]; 1033 ArrayRef<Record*> Order = RC.getOrder(); local 1036 AllocatableRegs.insert(Order.begin(), Order.end()); 1160 << " const ArrayRef<MCPhysReg> Order[] [all...] |
H A D | CodeGenRegisters.cpp | 697 SetTheory::RecSet Order; local 699 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); 700 Orders[1 + i].append(Order.begin(), Order.end()); 702 while (!Order.empty()) { 703 CodeGenRegister *Reg = RegBank.getReg(Order.back()); 704 Order.pop_back(); 823 // Order by ascending spill size. 829 // Order by ascending spill alignment. 835 // Order b [all...] |
/freebsd-9.3-release/contrib/llvm/tools/clang/lib/CodeGen/ |
H A D | CGAtomic.cpp | 190 uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) { 209 CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order); 222 Load->setAtomic(Order); 237 Store->setAtomic(Order); 300 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order); 354 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0; local 364 Order = EmitScalarExpr(E->getOrder()); 499 Args.add(RValue::get(Order), getContext().IntTy); 500 Order = OrderFail; 584 Args.add(RValue::get(Order), 188 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, llvm::Value *Dest, llvm::Value *Ptr, llvm::Value *Val1, llvm::Value *Val2, uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) argument [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 211 ArrayRef<MCPhysReg> Order, 227 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 243 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 247 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 248 unsigned Reg = Order[I]; 210 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const argument
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H A D | ARMBaseRegisterInfo.h | 131 ArrayRef<MCPhysReg> Order,
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/freebsd-9.3-release/contrib/llvm/lib/Support/ |
H A D | Dwarf.cpp | 624 const char *llvm::dwarf::ArrayOrderString(unsigned Order) { argument 625 switch (Order) {
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/freebsd-9.3-release/usr.bin/make/ |
H A D | parse.c | 166 Order, /* .ORDER */ enumerator in enum:__anon10800 225 { ".ORDER", Order, 0 }, 584 case Order: 896 case Order:
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/freebsd-9.3-release/contrib/llvm/lib/MC/ |
H A D | MachObjectWriter.cpp | 607 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder(); local 608 for (int i = 0, n = Order.size(); i != n ; ++i) { 609 const MCSectionData *SD = Order[i];
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