Searched refs:LiveRegs (Results 1 - 4 of 4) sorted by relevance

/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DExecutionDepsFix.cpp136 LiveReg *LiveRegs; member in class:__anon2121::ExeDepsFix
182 // LiveRegs manipulations.
258 /// Set LiveRegs[rx] = dv, updating reference counts.
261 assert(LiveRegs && "Must enter basic block first.");
263 if (LiveRegs[rx].Value == dv)
265 if (LiveRegs[rx].Value)
266 release(LiveRegs[rx].Value);
267 LiveRegs[rx].Value = retain(dv);
273 assert(LiveRegs && "Must enter basic block first.");
274 if (!LiveRegs[r
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H A DRegisterPressure.cpp169 LiveRegs.PhysRegs.clear();
170 LiveRegs.VirtRegs.clear();
203 LiveRegs.PhysRegs.setUniverse(TRI->getNumRegs());
204 LiveRegs.VirtRegs.setUniverse(MRI->getNumVirtRegs());
243 P.LiveInRegs.reserve(LiveRegs.PhysRegs.size() + LiveRegs.VirtRegs.size());
244 P.LiveInRegs.append(LiveRegs.PhysRegs.begin(), LiveRegs.PhysRegs.end());
246 LiveRegs.VirtRegs.begin(), E = LiveRegs
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H A DPostRASchedulerList.cpp124 /// LiveRegs - true if the register is live.
125 BitVector LiveRegs; member in class:__anon2162::SchedulePostRATDList
209 LiveRegs(TRI->getNumRegs()), EndIndex(0)
430 LiveRegs.reset();
441 LiveRegs.set(*SubRegs);
455 if (LiveRegs.test(MO.getReg())) {
467 if (LiveRegs.test(*SubRegs)) {
502 LiveRegs.clearBitsNotInMask(MO.getRegMask());
513 LiveRegs.reset(*SubRegs);
531 if (LiveRegs
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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h279 LiveRegSet LiveRegs;

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