Searched refs:L1_S_C (Results 1 - 5 of 5) sorted by relevance

/freebsd-9.3-release/sys/arm/include/
H A Dpte.h202 #define L1_S_C 0x00000008 /* cacheable Section */ macro
H A Dpmap.h259 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
260 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\
/freebsd-9.3-release/sys/arm/arm/
H A Dlocore.S223 MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
225 MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
H A Dpmap.c470 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
485 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
489 pte_l1_s_cache_mode_pt = L1_S_C;
535 pte_l1_s_cache_mode = L1_S_C;
539 pte_l1_s_cache_mode_pt = L1_S_C;
557 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
561 pte_l1_s_cache_mode_pt = L1_S_C;
581 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
600 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
609 pte_l1_s_cache_mode_pt = L1_S_C;
[all...]
H A Delf_trampoline.c555 pd[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)|

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