Searched refs:Inst (Results 1 - 25 of 180) sorted by relevance

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/freebsd-9.3-release/contrib/llvm/lib/MC/
H A DMCInstrAnalysis.cpp13 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
/freebsd-9.3-release/contrib/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h31 virtual bool isBranch(const MCInst &Inst) const {
32 return Info->get(Inst.getOpcode()).isBranch();
35 virtual bool isConditionalBranch(const MCInst &Inst) const {
36 return Info->get(Inst.getOpcode()).isConditionalBranch();
39 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
40 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
43 virtual bool isIndirectBranch(const MCInst &Inst) const {
44 return Info->get(Inst.getOpcode()).isIndirectBranch();
47 virtual bool isCall(const MCInst &Inst) const {
48 return Info->get(Inst
[all...]
H A DMCInstBuilder.h23 MCInst Inst; member in class:llvm::MCInstBuilder
28 Inst.setOpcode(Opcode);
33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
62 return Inst;
H A DMCCodeEmitter.h35 /// EncodeInstruction - Encode the given \p Inst to bytes on the output
37 virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,
/freebsd-9.3-release/contrib/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
97 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
100 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
103 static DecodeStatus Decode2RInstruction(MCInst &Inst,
108 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
113 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
118 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
123 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
128 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
210 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
222 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
234 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
245 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
286 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
356 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
369 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
382 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
395 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
409 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
422 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
435 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
449 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
520 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
534 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
548 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
561 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
574 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
587 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
600 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
614 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
629 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
643 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
657 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
677 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
691 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
711 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
730 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp50 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
56 Inst.addOperand(MCOperand::CreateReg(RegNo));
60 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
63 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs);
66 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
69 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs);
72 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
75 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs);
78 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
81 return decodeRegisterClass(Inst, RegN
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp50 Instruction *Inst; member in struct:__anon2629::SimpleValue
52 SimpleValue(Instruction *I) : Inst(I) {
53 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
57 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() ||
58 Inst == DenseMapInfo<Instruction*>::getTombstoneKey();
61 static bool canHandle(Instruction *Inst) { argument
63 if (CallInst *CI = dyn_cast<CallInst>(Inst))
65 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
66 isa<GetElementPtrInst>(Inst) || is
88 Instruction *Inst = Val.Inst; local
193 Instruction *Inst; member in struct:__anon2630::CallValue
204 canHandle(Instruction *Inst) argument
230 Instruction *Inst = Val.Inst; local
422 Instruction *Inst = I++; local
527 << *Inst << '\\n'); local
[all...]
H A DSink.cpp58 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
59 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const;
74 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument
80 for (Value::use_iterator I = Inst->use_begin(),
81 E = Inst->use_end(); I != E; ++I) {
136 Instruction *Inst = I; // The instruction to sink. local
144 if (isa<DbgInfoIntrinsic>(Inst))
147 if (SinkInstruction(Inst, Stores))
156 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument
159 if (Inst
180 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const argument
219 SinkInstruction(Instruction *Inst, SmallPtrSet<Instruction *, 8> &Stores) argument
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
85 static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
87 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
304 DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
315 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
325 DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
337 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
348 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
359 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
371 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
382 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
393 DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
402 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
413 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
421 DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
433 DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo, unsigned RegID, const void *Decoder) argument
444 DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
451 DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
458 DecodeDTripleRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
465 DecodeQTripleRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
472 DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
479 DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
486 DecodeAddrRegExtendOperand(llvm::MCInst &Inst, unsigned OptionHiS, uint64_t Address, const void *Decoder) argument
499 DecodeBitfield32ImmOperand(llvm::MCInst &Inst, unsigned Imm6Bits, uint64_t Address, const void *Decoder) argument
512 DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, unsigned Imm6Bits, uint64_t Address, const void *Decoder) argument
524 DecodeFPZeroOperand(llvm::MCInst &Inst, unsigned RmBits, uint64_t Address, const void *Decoder) argument
534 DecodeShiftRightImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
541 DecodeShiftRightImm16(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
548 DecodeShiftRightImm32(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
555 DecodeShiftRightImm64(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
562 DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
572 DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
582 DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
592 DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
603 DecodeMoveWideImmOperand(llvm::MCInst &Inst, unsigned FullImm, uint64_t Address, const void *Decoder) argument
618 DecodeLogicalImmOperand(llvm::MCInst &Inst, unsigned Bits, uint64_t Address, const void *Decoder) argument
631 DecodeRegExtendOperand(llvm::MCInst &Inst, unsigned ShiftAmount, uint64_t Address, const void *Decoder) argument
643 Decode32BitShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, uint64_t Address, const void *Decoder) argument
655 DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
747 DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
771 DecodeLDSTPairInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
855 DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument
891 DecodeNamedImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
906 DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
919 DecodeMRSOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
927 DecodeMSROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
935 DecodeSingleIndexedInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1006 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, uint64_t Address, const void *Decoder) argument
1030 DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1118 DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1542 DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
427 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
436 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
449 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
460 DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
470 DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
477 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
489 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
501 DecodeFGRH32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
513 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
524 DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
535 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
557 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
573 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
591 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
609 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
628 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
639 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
652 DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
664 DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
676 DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
688 DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
700 DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
712 DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
724 DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
736 DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
748 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
758 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
768 DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
778 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
787 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
795 DecodeLSAImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
804 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
815 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigne
876 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
887 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
900 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
914 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
926 DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
941 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
971 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
991 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1012 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1022 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1045 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1065 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1086 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1098 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1112 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1121 DecodeSOImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1130 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1167 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1202 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1239 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1263 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1288 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1315 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1465 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1570 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1614 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1805 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1834 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1857 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1948 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1995 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2037 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2061 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2088 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2116 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2136 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2155 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2161 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2188 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2214 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2231 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2505 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2518 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2533 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2546 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2556 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2827 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2874 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2922 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2957 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3012 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3057 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3076 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3082 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3088 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3094 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3100 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3136 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3160 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3168 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3176 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3184 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3199 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3213 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3223 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3231 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3259 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3330 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3394 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3459 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3498 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3543 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3557 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3572 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument
3587 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3600 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3646 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3707 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3733 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3744 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3769 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3780 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3793 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3817 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3832 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3848 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3890 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3922 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3930 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3953 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3962 DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3971 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3978 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3999 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4024 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4049 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4077 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4102 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4127 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4194 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4260 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4327 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4391 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4461 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4525 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4606 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4678 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4704 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4730 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4750 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4787 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4821 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
4836 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument
4847 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4874 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4904 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4934 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4961 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-9.3-release/contrib/llvm/utils/TableGen/
H A DInstrInfoEmitter.cpp55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument
91 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
100 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
104 OperandList.push_back(Inst.Operands[i]);
106 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
107 OperandList.push_back(Inst.Operands[i]);
137 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOp"))
142 if (Inst
210 const CodeGenInstruction *Inst = NumberedInstructions[i]; local
370 Record *Inst = (*II)->TheDef; local
468 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate
21 Inst(unsigned Opc, unsigned ImmOpnd);
23 typedef SmallVector<Inst, 7 > InstSeq;
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp240 void cvtThumbMultiply(MCInst &Inst,
242 void cvtThumbBranches(MCInst &Inst,
245 bool validateInstruction(MCInst &Inst,
247 bool processInstruction(MCInst &Inst,
289 unsigned checkTargetMatchPredicate(MCInst &Inst);
1528 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
1531 Inst.addOperand(MCOperand::CreateImm(0));
1533 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1535 Inst.addOperand(MCOperand::CreateExpr(Expr));
1538 void addCondCodeOperands(MCInst &Inst, unsigne argument
1545 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument
1550 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument
1555 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument
1560 addITMaskOperands(MCInst &Inst, unsigned N) const argument
1565 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument
1570 addCCOutOperands(MCInst &Inst, unsigned N) const argument
1575 addRegOperands(MCInst &Inst, unsigned N) const argument
1580 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument
1590 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument
1601 addShifterImmOperands(MCInst &Inst, unsigned N) const argument
1607 addRegListOperands(MCInst &Inst, unsigned N) const argument
1615 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument
1619 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument
1623 addRotImmOperands(MCInst &Inst, unsigned N) const argument
1629 addBitfieldOperands(MCInst &Inst, unsigned N) const argument
1640 addImmOperands(MCInst &Inst, unsigned N) const argument
1645 addFBits16Operands(MCInst &Inst, unsigned N) const argument
1651 addFBits32Operands(MCInst &Inst, unsigned N) const argument
1657 addFPImmOperands(MCInst &Inst, unsigned N) const argument
1664 addImm8s4Operands(MCInst &Inst, unsigned N) const argument
1672 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument
1680 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument
1688 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument
1696 addImm1_16Operands(MCInst &Inst, unsigned N) const argument
1704 addImm1_32Operands(MCInst &Inst, unsigned N) const argument
1712 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument
1721 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument
1730 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument
1738 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument
1746 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument
1754 addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const argument
1765 addThumbMemPCOperands(MCInst &Inst, unsigned N) const argument
1785 addARMSOImmNotOperands(MCInst &Inst, unsigned N) const argument
1793 addARMSOImmNegOperands(MCInst &Inst, unsigned N) const argument
1801 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument
1806 addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const argument
1811 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument
1816 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument
1822 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument
1838 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument
1844 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument
2062 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument
2069 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument
2076 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument
2083 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument
2094 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument
2106 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument
2112 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument
2123 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument
2128 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument
2133 addVecListOperands(MCInst &Inst, unsigned N) const argument
2138 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument
2144 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument
2149 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument
2154 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument
2159 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument
2167 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument
2179 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument
2193 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument
2207 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument
2221 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument
4140 cvtThumbMultiply(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4157 cvtThumbBranches(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
5286 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
5302 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument
5313 instIsBreakpoint(const MCInst &Inst) argument
5323 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
5848 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
7620 checkTargetMatchPredicate(MCInst &Inst) argument
7668 MCInst Inst; local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Transforms/ObjCARC/
H A DObjCARCExpand.cpp98 Instruction *Inst = &*I; local
100 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n");
102 switch (GetBasicInstructionClass(Inst)) {
114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0);
115 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n"
117 Inst->replaceAllUsesWith(Value);
H A DDependencyAnalysis.cpp35 llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument
48 ImmutableCallSite CS = static_cast<const Value *>(Inst);
72 llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument
80 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) {
86 } else if (ImmutableCallSite CS = static_cast<const Value *>(Inst)) {
95 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
105 for (User::const_op_iterator OI = Inst->op_begin(), OE = Inst->op_end();
114 /// Test if there can be dependencies on Inst through Arg. This function only
117 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst, argument
237 Instruction *Inst = --LocalStartPos; local
[all...]
H A DDependencyAnalysis.h61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg,
67 CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA,
73 CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
H A DObjCARCAPElim.cpp98 Instruction *Inst = I++; local
99 switch (GetBasicInstructionClass(Inst)) {
101 Push = Inst;
106 if (Push && cast<CallInst>(Inst)->getArgOperand(0) == Push) {
110 " Pop: " << *Inst << "\n"
112 Inst->eraseFromParent();
118 if (MayAutorelease(ImmutableCallSite(Inst)))
H A DObjCARCContract.cpp227 Instruction *Inst = I;
228 if (Inst == Release) {
233 InstructionClass Class = GetBasicInstructionClass(Inst);
242 if (CanUse(Inst, Load, PA, Class))
244 } else if (AA->getModRefInfo(Inst, Loc) & AliasAnalysis::Mod) {
247 Store = dyn_cast<StoreInst>(Inst);
344 Instruction *Inst = &*I++; local
346 DEBUG(dbgs() << "ObjCARCContract: Visiting: " << *Inst << "\n");
350 InstructionClass Class = GetBasicInstructionClass(Inst);
357 if (ContractAutorelease(F, Inst, Clas
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Analysis/
H A DPHITransAddr.cpp25 static bool CanPHITrans(Instruction *Inst) { argument
26 if (isa<PHINode>(Inst) ||
27 isa<GetElementPtrInst>(Inst))
30 if (isa<CastInst>(Inst) &&
31 isSafeToSpeculativelyExecute(Inst))
34 if (Inst->getOpcode() == Instruction::Add &&
35 isa<ConstantInt>(Inst->getOperand(1)))
118 Instruction *Inst = dyn_cast<Instruction>(Addr); local
119 return Inst == 0 || CanPHITrans(Inst);
149 Instruction *Inst = dyn_cast<Instruction>(V); local
[all...]
H A DDelinearization.cpp72 static Value *getPointerOperand(Instruction &Inst) { argument
73 if (LoadInst *Load = dyn_cast<LoadInst>(&Inst))
75 else if (StoreInst *Store = dyn_cast<StoreInst>(&Inst))
77 else if (GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(&Inst))
85 Instruction *Inst = &(*I); local
88 if (!isa<StoreInst>(Inst) && !isa<LoadInst>(Inst) &&
89 !isa<GetElementPtrInst>(Inst))
92 const BasicBlock *BB = Inst->getParent();
96 const SCEV *AccessFn = SE->getSCEVAtScope(getPointerOperand(*Inst),
[all...]
H A DMemDepPrinter.cpp102 Instruction *Inst = &*I; local
104 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory())
107 MemDepResult Res = MDA.getDependency(Inst);
109 Deps[Inst].insert(std::make_pair(getInstTypePair(Res),
111 } else if (CallSite CS = cast<Value>(Inst)) {
115 DepSet &InstDeps = Deps[Inst];
123 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
126 Deps[Inst].insert(std::make_pair(getInstTypePair(0, Unknown),
132 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
162 const Instruction *Inst = &*I; local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp66 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0); local
67 MAI->addInitialFrameState(Inst);
125 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
126 if (Inst.getOpcode() == AArch64::Bcc
127 && Inst.getOperand(0).getImm() == A64CC::AL)
129 return MCInstrAnalysis::isUnconditionalBranch(Inst);
132 virtual bool isConditionalBranch(const MCInst &Inst) const {
133 if (Inst.getOpcode() == AArch64::Bcc
134 && Inst.getOperand(0).getImm() == A64CC::AL)
136 return MCInstrAnalysis::isConditionalBranch(Inst);
139 evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const argument
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp210 void ProcessInstruction(MCInst &Inst,
392 void addRegOperands(MCInst &Inst, unsigned N) const { argument
396 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { argument
398 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
401 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { argument
403 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
406 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { argument
408 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
411 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { argument
413 Inst
416 addRegGxRCOperands(MCInst &Inst, unsigned N) const argument
423 addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const argument
430 addRegF4RCOperands(MCInst &Inst, unsigned N) const argument
435 addRegF8RCOperands(MCInst &Inst, unsigned N) const argument
440 addRegVRRCOperands(MCInst &Inst, unsigned N) const argument
445 addRegCRBITRCOperands(MCInst &Inst, unsigned N) const argument
450 addRegCRRCOperands(MCInst &Inst, unsigned N) const argument
455 addCRBitMaskOperands(MCInst &Inst, unsigned N) const argument
460 addImmOperands(MCInst &Inst, unsigned N) const argument
468 addBranchTargetOperands(MCInst &Inst, unsigned N) const argument
476 addTLSRegOperands(MCInst &Inst, unsigned N) const argument
576 ProcessInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
862 MCInst Inst; local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterDwarf.cpp172 void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
173 switch (Inst.getOperation()) {
177 OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
180 OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
183 OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
186 OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
189 OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst
[all...]

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