Searched refs:DAG (Results 1 - 25 of 96) sorted by relevance

1234

/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DSIISelLowering.h1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
11 /// \brief SI DAG Lowering interface definition
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
27 SelectionDAG &DAG) const;
28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
30 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
31 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) cons
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H A DR600ISelLowering.h1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
11 /// \brief R600 DAG Lowering interface definition
29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
33 SelectionDAG &DAG) const;
39 SDLoc DL, SelectionDAG &DAG,
48 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
53 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
56 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
59 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) cons
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H A DAMDGPUISelLowering.h28 void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
31 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
37 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
40 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
41 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
45 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
49 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
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H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
246 SDLoc DL, SelectionDAG &DAG) const {
247 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
254 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
262 // AMDIL DAG lowering
263 case ISD::SDIV: return LowerSDIV(Op, DAG);
264 case ISD::SREM: return LowerSREM(Op, DAG);
265 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
266 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
267 // AMDGPU DAG lowerin
306 ExtractVectorElements(SDValue Op, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Args, unsigned Start, unsigned Count) const argument
735 getOriginalFunctionArgs( SelectionDAG &DAG, const Function *F, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<ISD::InputArg> &OrigIns) const argument
787 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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H A DSIISelLowering.cpp1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
11 /// \brief Custom DAG lowering for SI
166 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, argument
169 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
170 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
172 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
174 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
175 DAG.getConstant(Offset, MVT::i64));
176 return DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, Chain, Ptr,
187 SDLoc DL, SelectionDAG &DAG,
182 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
850 SelectionDAG &DAG = DCI.DAG; local
974 getRegClassForNode( SelectionDAG &DAG, const SDValue &Op) const argument
1027 fitsRegClass(SelectionDAG &DAG, const SDValue &Op, unsigned RegClass) const argument
1038 ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, unsigned RegClass, bool &ScalarSlotUsed) const argument
1392 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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H A DR600ISelLowering.cpp1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
11 /// \brief Custom DAG lowering for R600
505 // Custom DAG Lowering Operations
508 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
509 MachineFunction &MF = DAG.getMachineFunction();
512 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
514 case ISD::FSIN: return LowerTrig(Op, DAG);
515 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
516 case ISD::STORE: return LowerSTORE(Op, DAG);
517 case ISD::LOAD: return LowerLOAD(Op, DAG);
825 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, SDLoc DL, unsigned DwordOffset) const argument
1338 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1392 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap<unsigned, unsigned> &RemapSwizzle) argument
1434 ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap<unsigned, unsigned> &RemapSwizzle) argument
1501 SelectionDAG &DAG = DCI.DAG; local
1714 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp33 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, argument
49 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,
50 DAG.getConstant(Size, PtrVT),
51 DAG.getConstant(Size / 256, PtrVT));
52 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
53 DAG.getConstant(Size, PtrVT));
57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument
66 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
74 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument
81 return DAG
87 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Dst, SDValue Byte, SDValue Size, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument
159 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument
183 addIPMSequence(SDLoc DL, SDValue Glue, SelectionDAG &DAG) argument
193 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
208 EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const argument
238 EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const argument
249 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
266 getBoundedStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue Limit) argument
279 EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const argument
286 EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const argument
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H A DSystemZISelLowering.h1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
11 // selection DAG.
223 SelectionDAG &DAG) const LLVM_OVERRIDE;
228 SelectionDAG &DAG) const LLVM_OVERRIDE;
235 SDLoc DL, SelectionDAG &DAG,
246 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
253 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
254 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
255 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
257 SelectionDAG &DAG) cons
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/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp30 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, argument
55 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
64 CallLoweringInfo CLI(Chain, Type::getVoidTy(*DAG.getContext()),
68 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args,
69 DAG, dl);
111 Count = DAG.getIntPtrConstant(SizeVal);
117 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
121 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
126 Count = DAG
176 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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H A DX86ISelLowering.h1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
11 // selection DAG.
29 // X86 Specific DAG Nodes
541 SelectionDAG &DAG) const;
583 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
589 SelectionDAG &DAG) const;
612 /// DAG node.
624 const SelectionDAG &DAG,
635 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
655 SelectionDAG &DAG) cons
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/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
11 // selection DAG.
79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
82 /// DAG node.
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) cons
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/freebsd-9.3-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
97 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
103 SelectionDAG &DAG) const;
106 // DAG node.
125 SDLoc dl, SelectionDAG &DAG,
133 SDLoc dl, SelectionDAG &DAG,
138 SDLoc dl, SelectionDAG &DAG,
140 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
142 SelectionDAG &DAG) cons
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H A DXCoreISelLowering.cpp1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
196 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
199 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
200 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
201 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
202 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
203 case ISD::LOAD: return LowerLOAD(Op, DAG);
204 case ISD::STORE: return LowerSTORE(Op, DAG);
205 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
206 case ISD::VAARG: return LowerVAARG(Op, DAG);
388 isWordAligned(SDValue Value, SelectionDAG &DAG) argument
879 SelectionDAG &DAG = CLI.DAG; local
910 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1036 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1070 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1094 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1391 SelectionDAG &DAG = DCI.DAG; local
1583 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
11 // selection DAG.
49 // load instruction. This prevents the DAG combiner folding a truncate to
64 /// these are pre-encoded since DAG matching can't cope with combining LSB
101 /// these are pre-encoded since DAG matching can't cope with combining LSB
218 SDLoc dl, SelectionDAG &DAG,
225 SDLoc dl, SelectionDAG &DAG) const;
233 SDLoc dl, SelectionDAG &DAG,
236 bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &Res) const;
238 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.h1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
11 // selection DAG.
221 SelectionDAG &DAG) const;
224 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
230 SelectionDAG &DAG) const;
233 // DAG node.
251 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
258 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, argument
262 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, T
278 getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
292 getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
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H A DMipsSEISelLowering.cpp1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
262 SelectionDAG &DAG) const {
264 case ISD::LOAD: return lowerLOAD(Op, DAG);
265 case ISD::STORE: return lowerSTORE(Op, DAG);
266 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
267 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
268 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
269 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
270 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
271 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
429 performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
449 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
564 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
684 performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
697 genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument
735 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL) argument
748 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget *Subtarget) argument
772 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
795 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
841 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
870 performSETCCCombine(SDNode *N, SelectionDAG &DAG) argument
883 performVSELECTCombine(SDNode *N, SelectionDAG &DAG) argument
939 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget *Subtarget) argument
968 SelectionDAG &DAG = DCI.DAG; local
1002 N->printrWithDepth(dbgs(), &DAG); local
1004 Val.getNode()->printrWithDepth(dbgs(), &DAG); local
1176 initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) argument
1184 extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) argument
1202 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1251 lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1264 lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) argument
1293 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) argument
1297 getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG) argument
1333 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument
1376 lowerMSABitClear(SDValue Op, SelectionDAG &DAG) argument
1386 lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) argument
2021 lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) argument
2089 lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) argument
2287 lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2345 lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2375 lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2405 lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2435 lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2466 lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2492 lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2516 lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
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H A DMipsSEISelLowering.h1 //===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
35 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
67 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
68 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
71 SelectionDAG &DAG) const;
73 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
74 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
75 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
76 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
77 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) cons
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp29 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, argument
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
68 DAG.getConstant(SrcOff, MVT::i32)),
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
78 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
80 DAG.getConstant(DstOff, MVT::i32)),
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
105 Loads[i] = DAG
143 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp36 SelectionDAG& DAG; member in class:__anon2182::VectorLegalizer
84 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
90 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
91 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) {
113 DAG.AssignTopologicalOrder();
114 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
115 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
119 SDValue OldRoot = DAG.getRoot();
121 DAG.setRoot(LegalizedNodes[OldRoot]);
126 DAG
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H A DLegalizeVectorTypes.cpp35 N->dump(&DAG);
43 N->dump(&DAG);
133 return DAG.getNode(N->getOpcode(), SDLoc(N),
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
153 return DAG.getNode(ISD::BITCAST, SDLoc(N),
163 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
170 return DAG.getConvertRndSat(NewVT, SDLoc(N),
171 Op0, DAG.getValueType(NewVT),
172 DAG.getValueType(Op0.getValueType()),
179 return DAG
2481 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument
2534 BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, SmallVectorImpl<SDValue> &LdOps, unsigned Start, unsigned End) argument
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H A DLegalizeIntegerTypes.cpp36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
47 N->dump(&DAG); dbgs() << "\n";
156 return DAG.getNode(ISD::AssertSext, SDLoc(N),
163 return DAG.getNode(ISD::AssertZext, SDLoc(N),
168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
182 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
196 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG
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H A DLegalizeDAG.cpp53 SelectionDAG &DAG; member in class:__anon2180::SelectionDAGLegalize
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
163 DAG.RemoveDeadNode(N);
169 DAG.ReplaceAllUsesWith(Old, New);
173 DAG.ReplaceAllUsesWith(Old, New);
177 DAG.ReplaceAllUsesWith(Old, New);
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
218 DAG(da
304 ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, const TargetLowering &TLI, SelectionDAGLegalize *DAGLegalize) argument
430 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, const TargetLowering &TLI, SDValue &ValResult, SDValue &ChainResult) argument
740 DAG, TLI, this); local
850 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); local
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H A DSelectionDAGBuilder.cpp1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
76 // Limit the width of DAG chains. This is important in general to prevent
77 // prevent DAG-based analysis from blowing up. For example, alias analysis and
80 // future analyses are likely to have the same behavior. Limiting DAG width is
92 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
101 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, argument
107 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
125 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
128 EVT HalfVT = EVT::getIntegerVT(*DAG
222 getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V) argument
339 getCopyToParts(SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) argument
471 getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V) argument
677 getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, SDLoc dl, SDValue &Chain, SDValue *Flag, const Value *V) const argument
777 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, SDValue *Flag, const Value *V) const argument
830 AddInlineAsmOperands(unsigned Code, bool HasMatching, unsigned MatchingIdx, SelectionDAG &DAG, std::vector<SDValue> &Ops) const argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
83 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SelectionDAG &DAG) const;
118 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
133 SelectionDAG &DAG) const;
137 SelectionDAG &DAG) const;
149 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
151 SDValue getParamSymbol(SelectionDAG &DAG, in
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/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
11 // selection DAG.
175 SDLoc DL, SelectionDAG &DAG) const {
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
194 DAG.getTarget(), RVLocs, *DAG
321 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
339 LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
539 LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
659 hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite *CS) argument
684 SelectionDAG &DAG = CLI.DAG; local
971 getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const argument
1712 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
2002 LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const argument
2163 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2179 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2196 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2225 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2253 LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2274 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2293 LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2330 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument
2366 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2386 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument
2409 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2433 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument
2440 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2479 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument
2488 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument
2521 LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) argument
2550 LowerF128Load(SDValue Op, SelectionDAG &DAG) argument
2602 LowerF128Store(SDValue Op, SelectionDAG &DAG) argument
2646 LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) argument
2677 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
2728 LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
2773 LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) argument
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