Searched refs:CP_PACKET0 (Results 1 - 11 of 11) sorted by relevance

/freebsd-9.3-release/sys/dev/drm/
H A Dr300_cmdbuf.c74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
339 OUT_RING(CP_PACKET0(reg, sz - 1));
387 OUT_RING(CP_PACKET0(reg, sz - 1));
421 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
423 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
425 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
438 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_RE
[all...]
H A Dradeon_state.c437 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
439 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
469 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
477 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
481 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
488 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
495 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
498 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
505 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
507 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_
[all...]
H A Dradeon_drv.h1891 #define CP_PACKET0( reg, n ) \ macro
1908 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1910 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1917 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1919 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1926 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1928 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1936 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1938 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1944 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTA
[all...]
H A Dradeon_cp.c584 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
/freebsd-9.3-release/sys/dev/drm2/radeon/
H A Dr300_cmdbuf.c74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
335 OUT_RING(CP_PACKET0(reg, sz - 1));
379 OUT_RING(CP_PACKET0(reg, sz - 1));
410 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
412 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
414 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
427 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_RE
[all...]
H A Dradeon_state.c459 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
461 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
491 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
499 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
503 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
510 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
517 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
520 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
527 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
529 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_
[all...]
H A Dradeon_drv.h1911 #define CP_PACKET0( reg, n ) \ macro
1927 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1933 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1939 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1946 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1952 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1955 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1962 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1965 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1972 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTA
[all...]
H A Dr300d.h34 #define CP_PACKET0 0x00000000 macro
63 #define PACKET0(reg, n) (CP_PACKET0 | \
H A Drv515d.h177 #define CP_PACKET0 0x00000000 macro
203 #define PACKET0(reg, n) (CP_PACKET0 | \
H A Dradeon_cp.c609 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
618 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
659 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
H A Dr100d.h34 #define CP_PACKET0 0x00000000 macro
62 #define PACKET0(reg, n) (CP_PACKET0 | \

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