Searched refs:spill (Results 1 - 12 of 12) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSpiller.h21 /// Implementations are utility classes which insert spill or remat code on
29 /// spill - Spill the LRE.getParent() live interval.
30 virtual void spill(LiveRangeEdit &LRE) = 0;
35 /// Create and return a spiller that will insert spill code directly instead
H A DRegisterScavenging.h13 /// to spill slots.
45 /// Information on scavenged registers (held in a spill slot).
49 /// A spill slot used for scavenging a register post register allocation.
161 /// If \p AllowSpill is false, fail if a spill is required to make the
178 /// If \p AllowSpill is false, fail if a spill is required to make the
228 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
/freebsd-13-stable/contrib/subversion/subversion/libsvn_subr/
H A Dspillbuf.c2 * spillbuf.c : an in-memory buffer that can spill to disk
41 /* Pool for allocating blocks and the spill file. */
68 apr_file_t *spill; member in struct:svn_spillbuf_t
77 /* When false, do not delete the spill file when it is closed. */
82 spill file. */
85 /* The directory in which the spill file is created. */
88 /* The name of the temporary spill file. */
94 /* Embed the spill-buffer within the reader. */
194 return buf->spill;
197 /* Get a memblock from the spill
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/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_trampoline_powerpc64_asm.S10 # floating point, and vector parameters, so that we only spill those live ones.
151 # floating point, and vector parameters, so that we only spill those live ones.
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocBasic.cpp56 /// algorithm. It prioritizes live virtual registers by spill weight and spills
239 spiller().spill(LRE);
258 // Populate a list of physical register spill candidates.
271 // Only virtual registers in the way, we may be able to spill them.
281 // Try to spill another interfering reg with less spill weight.
288 "Interference after spill.");
293 // No other spill candidates were found, so spill the current VirtReg.
298 spiller().spill(LR
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H A DRegisterScavenging.cpp13 /// them to spill slots.
267 // Expire scavenge spill frameindex uses.
409 // we have to spill, and can only place the restore after From then
461 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
488 // trying to spill a smaller register, the large slot would be found
489 // first, thus making it impossible to spill the larger register later.
498 // We need to scavenge a register but have no spill slot, the target
507 // otherwise, use the emergency stack spill slot.
512 std::string Msg = std::string("Error while trying to spill ") +
514 ": Cannot scavenge register without an emergency spill slo
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H A DRegAllocFast.cpp89 bool Dirty = false; ///< Register needs spill.
224 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
255 // Allocate a new stack object for this spill location...
313 /// Insert spill instruction for \p AssignedReg before \p Before. Update
315 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, function in class:__anon3551::RegAllocFast
334 LLVM_DEBUG(dbgs() << "Inserting debug info due to spill:\n" << *NewDV);
423 // instruction, not on the spill.
427 spill(MI, LR.VirtReg, LR.PhysReg, SpillKill);
676 // Ignore the hint if we would have to spill a dirty register.
697 // Ignore the hint if we would have to spill
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H A DInlineSpiller.cpp77 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
78 cl::desc("Disable inline spill hoisting"));
115 /// siblings. To hoist a spill to another BB, we need to find out a live
116 /// sibling there and use it as the source of the new spill.
172 // Variables that are valid during spill(), but used by multiple methods.
178 // All registers to spill to StackSlot, including the main register.
208 void spill(LiveRangeEdit &) override;
252 // When spilling a virtual register, we also spill any snippets it is connected
258 // spill slots which can be important in tight loops.
344 LLVM_DEBUG(dbgs() << "\talso spill snippe
1124 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller
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H A DRegAllocPBQP.cpp13 // register assignment. If any variables are selected for spilling then spill
190 /// Set spill costs for each node in the PBQP reg-alloc graph.
196 // A minimum spill costs, so that register constraints can can be set
683 VRegSpiller.spill(LRE);
695 assert(!LI.empty() && "Empty spill range.");
784 // All intervals have a spill weight that is mostly proportional to the number
H A DRegAllocGreedy.cpp89 "split-spill-mode", cl::Hidden,
271 float MaxWeight = 0; ///< Maximum spill weight evicted.
904 // Never evict spill products. They cannot split or spill.
908 // register for it. This is indicated by an infinite spill weight. These
982 // Never evict spill products. They cannot split or spill.
1114 // hints, and only evict smaller spill weights.
1202 // Number of spill code instructions to insert.
1217 // Abort if the spill canno
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/freebsd-13-stable/crypto/openssl/crypto/bn/asm/
H A Dia64-mont.pl398 stf.spill [sp]=f16,-16
400 stf.spill [r17]=f17,32
403 stf.spill [r16]=f18,32
405 stf.spill [r17]=f19,32
408 stf.spill [r16]=f20,32
410 stf.spill [r17]=f21,32
413 stf.spill [r16]=f22
415 stf.spill [r17]=f23
/freebsd-13-stable/sys/contrib/openzfs/module/zfs/
H A Ddmu_recv.c107 boolean_t spill; /* DRR_FLAG_SPILL_BLOCK set */ member in struct:receive_writer_arg
596 /* raw receives require spill block allocation flag */
977 /* raw receives require spill block allocation flag */
1608 (!rwa->spill && DRR_OBJECT_HAS_SPILL(drro->drr_flags))) {
1711 dn_slots << DNODE_SHIFT, rwa->spill ?
1713 } else if (rwa->spill && !DRR_OBJECT_HAS_SPILL(drro->drr_flags)) {
1716 * may reference a spill block that is no longer allocated
2138 * This is an unmodified spill block which was added to the stream
2139 * to resolve an issue with incorrectly removing spill blocks. It
2143 if (rwa->spill
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