Searched refs:hasVSX (Results 1 - 9 of 9) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.h259 bool hasVSX() const { return HasVSX; } function in class:llvm::PPCSubtarget
321 return hasVSX() && isLittleEndian() && !hasP9Vector();
H A DPPCTargetTransformInfo.cpp625 if (ST->hasVSX()) {
635 return ST->hasVSX() ? VSXRC : VRRC;
638 return ST->hasVSX() ? VSXRC : FPRRC;
830 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
917 bool IsVSXType = ST->hasVSX() &&
927 if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType &&
952 if (IsVSXType || (ST->hasVSX() && IsAltivecType))
H A DPPCVSXCopy.cpp145 if (!STI.hasVSX())
H A DPPCVSXFMAMutate.cpp352 if (!STI.hasVSX())
H A DPPCRegisterInfo.cpp147 if (Subtarget.hasVSX())
204 if (Subtarget.hasVSX())
427 if (Subtarget.hasVSX()) {
H A DPPCISelLowering.cpp302 if (Subtarget.hasVSX())
616 if (Subtarget.hasVSX()) {
652 if (Subtarget.hasVSX()) {
802 if (Subtarget.hasVSX()) {
829 if (Subtarget.hasVSX()) {
961 // The predictor is `hasVSX` because altivec instruction has
3723 if (Subtarget.hasVSX())
4170 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
9308 ((Subtarget.hasVSX() && ElementSize == 64) ||
9325 if (Subtarget.hasVSX()
[all...]
H A DPPCVSXSwapRemoval.cpp197 if (!STI.hasVSX() || !STI.needsSwapsForVSXMemOps())
H A DPPCISelDAGToDAG.cpp3858 Opc = Subtarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
3861 assert(Subtarget->hasVSX() && "__float128 requires VSX");
4151 getVCmpInst(VecVT.getSimpleVT(), CC, Subtarget->hasVSX(), Swap, Negate);
4158 CurDAG->SelectNodeTo(N, Subtarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR,
5088 if (Subtarget->hasVSX())
5116 if (Subtarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
H A DPPCInstrInfo.cpp2389 assert(Subtarget.hasVSX() &&
4246 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)

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