/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 35 MO.getSubReg() == SystemZ::subreg_l32 || 36 MO.getSubReg() == SystemZ::subreg_hl32) 39 MO.getSubReg() == SystemZ::subreg_h32 || 40 MO.getSubReg() == SystemZ::subreg_hh32) 115 if (MO->getSubReg()) 116 PhysReg = getSubReg(PhysReg, MO->getSubReg()); 117 if (VRRegMO->getSubReg()) 118 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ExpandSpecialInstrs.cpp | 223 Src0 = TRI.getSubReg(Src0, SubRegIndex); 224 Src1 = TRI.getSubReg(Src1, SubRegIndex); 229 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 230 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 238 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
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H A D | SIPreAllocateWWMRegs.cpp | 136 const unsigned SubReg = MO.getSubReg(); 138 PhysReg = TRI->getSubReg(PhysReg, SubReg);
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H A D | SIOptimizeExecMaskingPreRA.cpp | 123 unsigned CmpSubReg = AndCC->getSubReg(); 127 CmpSubReg = AndCC->getSubReg(); 146 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS); 170 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
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H A D | SIFoldOperands.cpp | 304 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); 486 SubDef && Sub->isReg() && !Sub->getSubReg() && 579 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) 602 if (RSUse->getSubReg() != RegSeqDstSubReg) 703 !UseMI->getOperand(1).getSubReg()) { 709 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); 845 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); 877 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { 885 if (UseOp.getSubReg() == AMDGPU::sub0) { 888 assert(UseOp.getSubReg() [all...] |
H A D | GCNRegBankReassign.cpp | 288 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); 309 Reg = TRI->getSubReg(Reg, SubReg); 321 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); 384 if (Bank != -1 && R == Reg && Op.getSubReg()) { 385 unsigned Offset = TRI->getChannelFromSubReg(Op.getSubReg()); 386 LaneBitmask LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()); 401 uint32_t Mask = getRegBankMask(R, Op.getSubReg(), 405 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask)); 467 PhysReg = TRI->getSubReg(PhysReg, AMDGPU::sub0);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) 32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { function in class:MCRegisterInfo
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitConst32AndConst64.cpp | 89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); 90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
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H A D | HexagonRDFOpt.cpp | 124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); 126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); 128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); 140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), 141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
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H A D | RDFCopy.cpp | 46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); 47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); 128 return S.getSubReg();
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H A D | HexagonSplitDouble.cpp | 259 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) 321 if (!Op.getSubReg()) 325 if (MI->getOperand(1).getSubReg() != 0) 444 if (Op.getSubReg()) 607 unsigned SR = Op.getSubReg(); 653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) 678 assert(!UpdOp.getSubReg() [all...] |
H A D | HexagonAsmPrinter.cpp | 136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? 463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); 464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); 540 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); 541 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); 552 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); 553 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); 566 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); 567 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
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H A D | HexagonExpandCondsets.cpp | 179 Sub(Op.getSubReg()) {} 324 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); 376 Register DR = Op.getReg(), DSR = Op.getSubReg(); 593 Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); 648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) 649 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); 653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) 675 Register DR = MD.getReg(), DSR = MD.getSubReg(); 885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); 887 PredOp.getSubReg()); [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | PeepholeOptimizer.cpp | 511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) 848 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); 851 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); 894 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); 931 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); 936 if (MODef.getSubReg()) 979 if (MOExtractedReg.getSubReg()) 987 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); 1056 if ((Src.SubReg = MOInsertedReg.getSubReg())) 1066 return MODef.getSubReg() [all...] |
H A D | CalcSpillWeights.cpp | 57 sub = mi->getOperand(0).getSubReg(); 59 hsub = mi->getOperand(1).getSubReg(); 61 sub = mi->getOperand(1).getSubReg(); 63 hsub = mi->getOperand(0).getSubReg(); 73 Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
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H A D | OptimizePHIs.cpp | 119 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() && 120 !SrcMI->getOperand(1).getSubReg() &&
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H A D | DetectDeadLanes.cpp | 162 unsigned SrcSubIdx = MO.getSubReg(); 201 unsigned MOSubReg = MO.getSubReg(); 297 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); 346 assert(Def.getSubReg() == 0 && 398 unsigned MOSubReg = MO.getSubReg(); 412 assert(Def.getSubReg() == 0 && 427 unsigned SubReg = MO.getSubReg(); 460 unsigned SubReg = MO.getSubReg();
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H A D | TargetRegisterInfo.cpp | 291 if (RCI.getSubReg() == Idx) 330 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 339 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 349 *BestPreA = IA.getSubReg(); 350 *BestPreB = IB.getSubReg();
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H A D | TargetInstrInfo.cpp | 178 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; 179 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); 180 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); 445 if (FoldOp.getSubReg() || LiveOp.getSubReg()) 519 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); 559 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) { 905 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() && 1277 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), 1303 InputReg.SubReg = MOReg.getSubReg(); [all...] |
H A D | LiveIntervalCalc.cpp | 68 unsigned SubReg = MO.getSubReg(); 168 unsigned SubReg = MO.getSubReg();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); 187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); 198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64); 199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), 146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) 148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), 150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), 152 SubReg = MI->getOperand(1).getSubReg();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXFMAMutate.cpp | 221 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); 222 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg(); 223 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg();
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H A D | PPCQPXLoadSplat.cpp | 105 Register SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 470 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 471 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 472 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 473 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 475 D0 = TRI->getSubReg(Reg, ARM::dsub_4); 476 D1 = TRI->getSubReg(Reg, ARM::dsub_5); 477 D2 = TRI->getSubReg(Reg, ARM::dsub_6); 478 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 480 D0 = TRI->getSubReg(Reg, ARM::dsub_3); 481 D1 = TRI->getSubReg(Re [all...] |