Searched refs:getSubReg (Results 1 - 25 of 130) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp35 MO.getSubReg() == SystemZ::subreg_l32 ||
36 MO.getSubReg() == SystemZ::subreg_hl32)
39 MO.getSubReg() == SystemZ::subreg_h32 ||
40 MO.getSubReg() == SystemZ::subreg_hh32)
115 if (MO->getSubReg())
116 PhysReg = getSubReg(PhysReg, MO->getSubReg());
117 if (VRRegMO->getSubReg())
118 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp223 Src0 = TRI.getSubReg(Src0, SubRegIndex);
224 Src1 = TRI.getSubReg(Src1, SubRegIndex);
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
230 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
H A DSIPreAllocateWWMRegs.cpp136 const unsigned SubReg = MO.getSubReg();
138 PhysReg = TRI->getSubReg(PhysReg, SubReg);
H A DSIOptimizeExecMaskingPreRA.cpp123 unsigned CmpSubReg = AndCC->getSubReg();
127 CmpSubReg = AndCC->getSubReg();
146 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS);
170 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
H A DSIFoldOperands.cpp304 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
486 SubDef && Sub->isReg() && !Sub->getSubReg() &&
579 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
602 if (RSUse->getSubReg() != RegSeqDstSubReg)
703 !UseMI->getOperand(1).getSubReg()) {
709 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
845 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
877 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
885 if (UseOp.getSubReg() == AMDGPU::sub0) {
888 assert(UseOp.getSubReg()
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H A DGCNRegBankReassign.cpp288 Reg = TRI->getSubReg(Reg, AMDGPU::sub0);
309 Reg = TRI->getSubReg(Reg, SubReg);
321 Reg = TRI->getSubReg(Reg, AMDGPU::sub0);
384 if (Bank != -1 && R == Reg && Op.getSubReg()) {
385 unsigned Offset = TRI->getChannelFromSubReg(Op.getSubReg());
386 LaneBitmask LM = TRI->getSubRegIndexLaneMask(Op.getSubReg());
401 uint32_t Mask = getRegBankMask(R, Op.getSubReg(),
405 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask));
467 PhysReg = TRI->getSubReg(PhysReg, AMDGPU::sub0);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { function in class:MCRegisterInfo
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
H A DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg()));
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg()));
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()),
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
H A DRDFCopy.cpp46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
128 return S.getSubReg();
H A DHexagonSplitDouble.cpp259 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
321 if (!Op.getSubReg())
325 if (MI->getOperand(1).getSubReg() != 0)
444 if (Op.getSubReg())
607 unsigned SR = Op.getSubReg();
653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
678 assert(!UpdOp.getSubReg()
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H A DHexagonAsmPrinter.cpp136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
540 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
541 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
552 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
553 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
566 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
567 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
H A DHexagonExpandCondsets.cpp179 Sub(Op.getSubReg()) {}
324 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
376 Register DR = Op.getReg(), DSR = Op.getSubReg();
593 Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
649 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
675 Register DR = MD.getReg(), DSR = MD.getSubReg();
885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
887 PredOp.getSubReg());
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
848 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg());
851 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
894 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
931 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg());
936 if (MODef.getSubReg())
979 if (MOExtractedReg.getSubReg())
987 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1056 if ((Src.SubReg = MOInsertedReg.getSubReg()))
1066 return MODef.getSubReg()
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H A DCalcSpillWeights.cpp57 sub = mi->getOperand(0).getSubReg();
59 hsub = mi->getOperand(1).getSubReg();
61 sub = mi->getOperand(1).getSubReg();
63 hsub = mi->getOperand(0).getSubReg();
73 Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
H A DOptimizePHIs.cpp119 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() &&
120 !SrcMI->getOperand(1).getSubReg() &&
H A DDetectDeadLanes.cpp162 unsigned SrcSubIdx = MO.getSubReg();
201 unsigned MOSubReg = MO.getSubReg();
297 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
346 assert(Def.getSubReg() == 0 &&
398 unsigned MOSubReg = MO.getSubReg();
412 assert(Def.getSubReg() == 0 &&
427 unsigned SubReg = MO.getSubReg();
460 unsigned SubReg = MO.getSubReg();
H A DTargetRegisterInfo.cpp291 if (RCI.getSubReg() == Idx)
330 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
339 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
349 *BestPreA = IA.getSubReg();
350 *BestPreB = IB.getSubReg();
H A DTargetInstrInfo.cpp178 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
179 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
180 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
445 if (FoldOp.getSubReg() || LiveOp.getSubReg())
519 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
559 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
905 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
1277 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1303 InputReg.SubReg = MOReg.getSubReg();
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H A DLiveIntervalCalc.cpp68 unsigned SubReg = MO.getSubReg();
168 unsigned SubReg = MO.getSubReg();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
152 SubReg = MI->getOperand(1).getSubReg();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp221 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
222 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg();
223 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg();
H A DPPCQPXLoadSplat.cpp105 Register SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp470 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
471 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
472 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
473 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
475 D0 = TRI->getSubReg(Reg, ARM::dsub_4);
476 D1 = TRI->getSubReg(Reg, ARM::dsub_5);
477 D2 = TRI->getSubReg(Reg, ARM::dsub_6);
478 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
480 D0 = TRI->getSubReg(Reg, ARM::dsub_3);
481 D1 = TRI->getSubReg(Re
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