Searched refs:getShiftType (Results 1 - 5 of 5) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
525 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL &&
H A DAArch64InstPrinter.cpp983 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
986 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
1554 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
H A DAArch64AddressingModes.h72 /// getShiftType - Extract the shift type.
73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { function in namespace:llvm::AArch64_AM
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp812 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5;
838 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31);
846 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63);
H A DAArch64ISelDAGToDAG.cpp2193 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
2199 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {

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