Searched refs:ctrl_reg (Results 1 - 6 of 6) sorted by relevance

/freebsd-13-stable/sys/dev/cpufreq/
H A Dichss.c63 struct resource *ctrl_reg; member in struct:ichss_softc
254 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
256 if (sc->ctrl_reg == NULL) {
344 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT;
352 ICH_SET_REG(sc->ctrl_reg, old_val | req_val);
356 new_val = ICH_GET_REG(sc->ctrl_reg);
384 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT;
/freebsd-13-stable/sys/arm/allwinner/
H A Daw_nmi.c80 uint8_t ctrl_reg; member in struct:aw_nmi_reg_cfg
94 .ctrl_reg = NMI_IRQ_CTRL_REG,
100 .ctrl_reg = NMI_IRQ_CTRL_REG,
106 .ctrl_reg = R_NMI_IRQ_CTRL_REG,
282 SC_NMI_WRITE(sc, sc->cfg->ctrl_reg, icfg);
H A Daxp209.c342 uint8_t ctrl_reg; member in struct:axp2xx_pins
352 .ctrl_reg = AXP2XX_GPIO0_CTRL,
359 .ctrl_reg = AXP2XX_GPIO1_CTRL,
366 .ctrl_reg = AXP209_GPIO2_CTRL,
376 .ctrl_reg = AXP2XX_GPIO0_CTRL,
383 .ctrl_reg = AXP2XX_GPIO0_CTRL,
955 error = axp2xx_read(dev, sc->pins[pin].ctrl_reg, &data, 1);
984 error = axp2xx_read(dev, sc->pins[pin].ctrl_reg, &data, 1);
991 error = axp2xx_write(dev, sc->pins[pin].ctrl_reg, data);
1011 error = axp2xx_read(dev, sc->pins[pin].ctrl_reg,
[all...]
H A Daxp81x.c208 uint8_t ctrl_reg; member in struct:__anon8347
1205 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1);
1234 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1);
1241 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data);
1261 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1);
1299 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1);
1314 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data);
1333 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1);
1351 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data);
/freebsd-13-stable/sys/dev/e1000/
H A De1000_82575.c1554 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; local
1578 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1579 ctrl_reg |= E1000_CTRL_SLU;
1583 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1619 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1627 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
H A De1000_ich8lan.c2487 u32 ctrl_reg = 0; local
2511 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2513 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2520 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);

Completed in 77 milliseconds