Searched refs:XLenVT (Results 1 - 4 of 4) sorted by relevance
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 31 MVT XLenVT) { 33 RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq); 36 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); 38 SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT); 40 Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm); 42 Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm); 73 MVT XLenVT = Subtarget->getXLenVT(); local 104 if (VT == XLenVT && ConstNode->isNullValue()) { 106 RISCV::X0, XLenVT); 111 if (XLenVT 30 selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm, MVT XLenVT) argument 198 MVT XLenVT = Subtarget->getXLenVT(); local 242 MVT XLenVT = Subtarget->getXLenVT(); local 290 MVT XLenVT = Subtarget->getXLenVT(); local [all...] |
H A D | RISCVSubtarget.h | 60 MVT XLenVT = MVT::i32; member in class:llvm::RISCVSubtarget 120 MVT getXLenVT() const { return XLenVT; }
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H A D | RISCVSubtarget.cpp | 41 XLenVT = MVT::i64;
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H A D | RISCVISelLowering.cpp | 81 MVT XLenVT = Subtarget.getXLenVT(); local 84 addRegisterClass(XLenVT, &RISCV::GPRRegClass); 97 setLoadExtAction(N, XLenVT, MVT::i1, Promote); 100 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); 103 setOperationAction(ISD::BR_CC, XLenVT, Expand); 104 setOperationAction(ISD::SELECT, XLenVT, Custom); 105 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); 127 setOperationAction(ISD::MUL, XLenVT, Expand); 128 setOperationAction(ISD::MULHS, XLenVT, Expand); 129 setOperationAction(ISD::MULHU, XLenVT, Expan 532 MVT XLenVT = Subtarget.getXLenVT(); local 568 MVT XLenVT = Subtarget.getXLenVT(); local 641 MVT XLenVT = Subtarget.getXLenVT(); local 674 MVT XLenVT = Subtarget.getXLenVT(); local 753 MVT XLenVT = Subtarget.getXLenVT(); local 1550 MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; local 1993 MVT XLenVT = Subtarget.getXLenVT(); local 2194 MVT XLenVT = Subtarget.getXLenVT(); local [all...] |
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