Searched refs:WaveSize (Results 1 - 4 of 4) sorted by relevance
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 269 unsigned WaveSize = ST.getWavefrontSize(); local 270 return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size(); 286 unsigned WaveSize = ST.getWavefrontSize(); local 292 if (NumLanes > WaveSize) 304 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); 306 // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and 312 if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
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H A D | AMDGPUSubtarget.cpp | 326 const unsigned WaveSize = getWavefrontSize(); 341 const unsigned MaxGroupNumWaves = (MaxWorkGroupSize + WaveSize - 1) / WaveSize;
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H A D | AMDGPURegisterBankInfo.cpp | 1249 auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2()); local 1250 auto ScaledSize = B.buildShl(IntPtrTy, AllocSize, WaveSize); 4249 unsigned WaveSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI); 4251 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); 4252 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize);
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H A D | SIISelLowering.cpp | 11613 unsigned WaveSize) { 11618 if (!IT || IT->getBitWidth() != WaveSize) 11652 Result = hasCFUser(U, Visited, WaveSize); 11612 hasCFUser(const Value *V, SmallPtrSet<const Value *, 16> &Visited, unsigned WaveSize) argument
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