Searched refs:WRITE4 (Results 1 - 25 of 65) sorted by relevance

123

/freebsd-13-stable/sys/mips/ingenic/
H A Djz4780_common.h35 #define WRITE4(_sc, _reg, _val) \ macro
H A Djz4780_intr.c92 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
111 WRITE4(sc, JZ_ICMCR0, (1u << irq));
113 WRITE4(sc, JZ_ICMCR1, (1u << (irq - 32)));
120 WRITE4(sc, JZ_ICMSR0, (1u << irq));
122 WRITE4(sc, JZ_ICMSR1, (1u << (irq - 32)));
177 WRITE4(sc, JZ_ICMR0, 0xFFFFFFFF);
178 WRITE4(sc, JZ_ICMR1, 0xFFFFFFFF);
H A Djz4780_pdma.c138 WRITE4(sc, PDMA_DIRQP, 0);
149 WRITE4(sc, PDMA_DCS(chan->index), 0);
214 WRITE4(sc, PDMA_DMAC, reg);
216 WRITE4(sc, PDMA_DMACP, 0);
241 WRITE4(sc, PDMA_DCS(chan->index), DCS_DES8);
242 WRITE4(sc, PDMA_DDA(chan->index),
245 WRITE4(sc, PDMA_DDS, (1 << chan->index));
248 WRITE4(sc, PDMA_DCS(chan->index), (DCS_DES8 | DCS_CTE));
258 WRITE4(sc, PDMA_DCS(chan->index), 0);
/freebsd-13-stable/sys/arm/freescale/vybrid/
H A Dvf_dcu4.c232 WRITE4(sc, DCU_INT_STATUS, reg);
297 WRITE4(sc, DCU_DISP_SIZE, reg);
302 WRITE4(sc, DCU_HSYN_PARA, reg);
307 WRITE4(sc, DCU_VSYN_PARA, reg);
309 WRITE4(sc, DCU_BGND, 0);
310 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div);
313 WRITE4(sc, DCU_SYNPOL, reg);
319 WRITE4(sc, DCU_THRESHOLD, reg);
322 WRITE4(sc, DCU_INT_MASK, 0xffffffff);
326 WRITE4(s
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H A Dvf_anadig.c143 WRITE4(sc, pll_ctrl, reg);
151 WRITE4(sc, pll_ctrl, reg);
171 WRITE4(sc, ANADIG_PLL4_CTRL, reg);
172 WRITE4(sc, ANADIG_PLL4_NUM, mfn);
173 WRITE4(sc, ANADIG_PLL4_DENOM, mfd);
211 WRITE4(sc, ANADIG_REG_3P0, reg);
216 WRITE4(sc, USB_MISC(0), reg);
220 WRITE4(sc, USB_MISC(1), reg);
H A Dvf_spi.c169 WRITE4(sc, SPI_MCR, reg);
173 WRITE4(sc, SPI_RSER, reg);
177 WRITE4(sc, SPI_MCR, reg);
195 WRITE4(sc, SPI_CTAR0, reg);
200 WRITE4(sc, SPI_CTAR0, reg);
225 WRITE4(sc, SPI_PUSHR, wreg);
236 WRITE4(sc, SPI_SR, reg);
H A Dvf_adc.c177 WRITE4(sc, ADC_HC0, reg);
214 WRITE4(sc, ADC_CFG, reg);
219 WRITE4(sc, ADC_GC, reg);
224 WRITE4(sc, ADC_HC0, reg);
H A Dvf_common.h33 #define WRITE4(_sc, _reg, _val) \ macro
/freebsd-13-stable/sys/arm/freescale/imx/
H A Dimx_gpt.c54 #define WRITE4(_sc, _r, _v) \ macro
59 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
61 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
195 WRITE4(sc, IMX_GPT_CR, 0);
196 WRITE4(sc, IMX_GPT_IR, 0);
206 WRITE4(sc, IMX_GPT_CR, ctlreg);
216 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
229 WRITE4(sc, IMX_GPT_PR, prescale);
232 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
235 WRITE4(s
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H A Dimx6_sdma.c67 #define WRITE4(_sc, _reg, _val) \ macro
100 WRITE4(sc, SDMAARM_INTR, pending);
118 WRITE4(sc, SDMAARM_HSTART, (1 << i));
143 WRITE4(sc, SDMAARM_HSTART, (1 << chn));
155 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));
222 WRITE4(sc, SDMAARM_EVTOVR, reg);
230 WRITE4(sc, SDMAARM_HOSTOVR, reg);
238 WRITE4(sc, SDMAARM_DSPOVR, reg);
266 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
267 WRITE4(s
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H A Dimx6_audmux.c57 #define WRITE4(_sc, _reg, _val) \ macro
108 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);
112 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
/freebsd-13-stable/sys/dev/flash/
H A Dcqspi.c85 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
161 WRITE4(sc, CQSPI_IRQSTAT, pending);
262 WRITE4(sc, CQSPI_FLASHCMDADDR, addr);
266 WRITE4(sc, CQSPI_FLASHCMD, reg);
269 WRITE4(sc, CQSPI_FLASHCMD, reg);
284 WRITE4(sc, CQSPI_FLASHCMD, reg);
286 WRITE4(sc, CQSPI_FLASHCMD, reg);
315 WRITE4(sc, CQSPI_FLASHCMD, reg);
318 WRITE4(sc, CQSPI_FLASHCMD, reg);
433 WRITE4(s
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/freebsd-13-stable/sys/arm/altera/socfpga/
H A Dsocfpga_a10_manager.c120 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
123 WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
129 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
178 WRITE4(sc, IMGCFG_CTRL_02, reg);
182 WRITE4(sc, IMGCFG_CTRL_02, reg);
187 WRITE4(sc, IMGCFG_CTRL_01, reg);
191 WRITE4(sc, IMGCFG_CTRL_00, reg);
196 WRITE4(sc, IMGCFG_CTRL_01, reg);
201 WRITE4(sc, IMGCFG_CTRL_02, reg);
211 WRITE4(s
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H A Dsocfpga_common.h36 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
H A Dsocfpga_manager.c227 WRITE4(sc, FPGAMGR_CTRL, reg);
232 WRITE4(sc, FPGAMGR_CTRL, reg);
237 WRITE4(sc, FPGAMGR_CTRL, reg);
248 WRITE4(sc, FPGAMGR_CTRL, reg);
256 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS);
261 WRITE4(sc, FPGAMGR_CTRL, reg);
273 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
276 WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
282 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
313 WRITE4(s
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/freebsd-13-stable/sys/dev/mmc/host/
H A Ddwmmc_samsung.c48 #define WRITE4(_sc, _reg, _val) \ macro
104 WRITE4(sc, EMMCP_MPSBEGIN0, 0);
105 WRITE4(sc, EMMCP_SEND0, 0);
106 WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT |
H A Ddwmmc.c91 #define WRITE4(_sc, _reg, _val) \ macro
220 WRITE4(sc, SDMMC_CTRL, reg);
430 WRITE4(sc, SDMMC_RINTSTS, reg);
445 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI |
447 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI);
714 WRITE4(sc, SDMMC_PWREN, (0 << slot));
716 WRITE4(sc, SDMMC_PWREN, (1 << slot));
740 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr);
743 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK);
744 WRITE4(s
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/freebsd-13-stable/sys/arm64/rockchip/clk/
H A Drk_clk_pll.c58 #define WRITE4(_clk, off, val) \ macro
94 WRITE4(clk, sc->gate_offset, val);
155 WRITE4(clk, sc->mode_reg, reg);
236 WRITE4(clk, sc->mode_reg, reg);
239 WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET |
251 WRITE4(clk, sc->base_offset, reg);
261 WRITE4(clk, sc->base_offset + 0x4, reg);
266 WRITE4(clk, sc->base_offset + 0x8, reg);
269 WRITE4(clk, sc->base_offset + 12,
295 WRITE4(cl
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/freebsd-13-stable/sys/dev/xilinx/
H A Daxi_quad_spi.c69 #define WRITE4(_sc, _reg, _val) \ macro
143 WRITE4(sc, SPI_SRR, SRR_RESET);
148 WRITE4(sc, SPI_CR, reg);
149 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */
152 WRITE4(sc, SPI_CR, reg);
166 WRITE4(sc, SPI_DTR, out_buf[i]);
201 WRITE4(sc, SPI_SSR, reg);
212 WRITE4(sc, SPI_SSR, reg);
/freebsd-13-stable/sys/dev/altera/pio/
H A Dpio.c63 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
128 WRITE4(sc, PIO_OUTSET, bit);
130 WRITE4(sc, PIO_OUTCLR, bit);
142 WRITE4(sc, PIO_INT_MASK, mask);
143 WRITE4(sc, PIO_DIR, dir);
/freebsd-13-stable/sys/arm/ti/clk/
H A Dti_clk_clkctrl.c75 #define WRITE4(_clk, off, val) \ macro
119 WRITE4(clk, sc->register_offset, val);
158 WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE);
160 WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE);
/freebsd-13-stable/sys/mips/mediatek/
H A Dmtk_intr_gic.c107 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val)) macro
127 WRITE4(sc, MTK_INTENA, (1u << (irq)));
134 WRITE4(sc, MTK_INTDIS, (1u << (irq)));
190 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
193 WRITE4(sc, MTK_INTTRIG, 0x00000000);
196 WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF);
202 WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0));
203 WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0));
H A Dmtk_intr_v1.c105 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
125 WRITE4(sc, MTK_INTENA, (1u << (irq)));
132 WRITE4(sc, MTK_INTDIS, (1u << (irq)));
186 WRITE4(sc, MTK_INTDIS, 0x7FFFFFFF);
189 WRITE4(sc, MTK_INTENA, 0x80000000);
192 WRITE4(sc, MTK_INTTYPE, 0x00000000);
H A Dmtk_intr_v2.c100 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
120 WRITE4(sc, MTK_INTENA, (1u << (irq)));
127 WRITE4(sc, MTK_INTDIS, (1u << (irq)));
181 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
184 WRITE4(sc, MTK_INTENA, 0x00000000);
187 WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF);
/freebsd-13-stable/sys/arm/allwinner/clkng/
H A Daw_clk_nkmp.c67 #define WRITE4(_clk, off, val) \ macro
116 WRITE4(clk, sc->offset, val);
137 WRITE4(clk, sc->offset, val);
212 WRITE4(clk, sc->offset, val);
219 WRITE4(clk, sc->offset, val);
227 WRITE4(clk, sc->offset, val);
233 WRITE4(clk, sc->offset, val);
240 WRITE4(clk, sc->offset, val);
300 WRITE4(clk, sc->offset, val);
308 WRITE4(cl
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