/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVCallLowering.h | 31 ArrayRef<Register> VRegs) const override; 34 ArrayRef<ArrayRef<Register>> VRegs) const override;
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H A D | RISCVCallLowering.cpp | 26 ArrayRef<Register> VRegs) const { 39 ArrayRef<ArrayRef<Register>> VRegs) const {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.h | 36 ArrayRef<Register> VRegs) const override; 39 ArrayRef<ArrayRef<Register>> VRegs) const override; 46 ArrayRef<Register> VRegs,
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H A D | ARMCallLowering.cpp | 238 const Value *Val, ArrayRef<Register> VRegs, 252 ArgInfo OrigRetInfo(VRegs, Val->getType()); 267 ArrayRef<Register> VRegs) const { 268 assert(!Val == VRegs.empty() && "Return value without a vreg"); 274 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret)) 417 ArrayRef<ArrayRef<Register>> VRegs) const { 451 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType()); 237 lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCallLowering.h | 44 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const; 50 ArrayRef<Register> VRegs) const override; 53 ArrayRef<ArrayRef<Register>> VRegs) const; 56 ArrayRef<ArrayRef<Register>> VRegs) const override;
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H A D | AMDGPUCallLowering.cpp | 312 const Value *Val, ArrayRef<Register> VRegs, 325 ArgInfo OrigRetInfo(VRegs, Val->getType()); 345 ArrayRef<Register> VRegs) const { 352 assert(!Val == VRegs.empty() && "Return value without a vreg"); 376 if (!lowerReturnVal(B, Val, VRegs, Ret)) 485 ArrayRef<ArrayRef<Register>> VRegs) const { 522 ArrayRef<Register> OrigArgRegs = VRegs[i]; 653 ArrayRef<ArrayRef<Register>> VRegs) const { 660 return lowerFormalArgumentsKernel(B, F, VRegs); 724 for (int I = 0, E = VRegs[Id 311 lowerReturnVal(MachineIRBuilder &B, const Value *Val, ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.h | 37 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs, 40 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs); 57 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs, 66 ArrayRef<Register> VRegs) const override; 69 ArrayRef<ArrayRef<Register>> VRegs) const override;
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H A D | MipsCallLowering.cpp | 39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs, argument 43 for (unsigned i = 0; i < VRegs.size(); ++i) 44 if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT)) 50 SmallVectorImpl<Register> &VRegs) { 52 std::reverse(VRegs.begin(), VRegs.end()); 57 SmallVector<Register, 4> VRegs; local 72 VRegs.clear(); 76 VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); 78 if (!handleSplit(VRegs, ArgLoc 49 setLeastSignificantFirst( SmallVectorImpl<Register> &VRegs) argument 200 handleSplit(SmallVectorImpl<Register> &VRegs, ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex, Register ArgsReg, const EVT &VT) argument 311 handleSplit(SmallVectorImpl<Register> &VRegs, ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex, Register ArgsReg, const EVT &VT) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.h | 32 ArrayRef<Register> VRegs) const override; 35 ArrayRef<ArrayRef<Register>> VRegs) const override;
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H A D | X86CallLowering.cpp | 189 ArrayRef<Register> VRegs) const { 190 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && 194 if (!VRegs.empty()) { 204 assert(VRegs.size() == SplitEVTs.size() && 209 ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)}; 213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); 329 ArrayRef<ArrayRef<Register>> VRegs) const { 351 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1) 354 ArgInfo OrigArg(VRegs[Id [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MIRVRegNamerUtils.cpp | 32 VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) { argument 44 for (const auto &VReg : VRegs) { 132 std::vector<NamedVReg> VRegs; local 140 // Look for instructions that define VRegs in operand 0. 145 VRegs.push_back( 149 return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false;
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H A D | SwiftErrorValueTracking.cpp | 181 SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs; local 186 VRegs.push_back(std::make_pair( 204 VRegs.size() >= 1 && 206 VRegs.begin(), VRegs.end(), 208 -> bool { return V.second != VRegs[0].second; }) != 209 VRegs.end(); 214 assert(!VRegs.empty() && 217 setCurrentVReg(MBB, SwiftErrorVal, VRegs[0].second); 229 assert(!VRegs [all...] |
H A D | MIRVRegNamerUtils.h | 62 /// For all the VRegs that are candidates for renaming, 65 getVRegRenameMap(const std::vector<NamedVReg> &VRegs);
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H A D | MachineVerifier.cpp | 2185 // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound 2206 SmallVector<unsigned, 0> VRegs; member in class:__anon3531::FilteringVRegSet 2217 // Double-duty the Filter: to maintain VRegs a set (and the join operation 2219 return Filter.filterAndAdd(RS, VRegs); 2221 using const_iterator = decltype(VRegs)::const_iterator; 2222 const_iterator begin() const { return VRegs.begin(); } 2223 const_iterator end() const { return VRegs.end(); } 2224 size_t size() const { return VRegs.size(); }
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.h | 37 ArrayRef<Register> VRegs, 43 ArrayRef<ArrayRef<Register>> VRegs) const override;
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H A D | AArch64CallLowering.cpp | 278 ArrayRef<Register> VRegs, 281 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && 285 if (!VRegs.empty()) { 297 assert(VRegs.size() == SplitEVTs.size() && 309 Register CurVReg = VRegs[i]; 445 ArrayRef<ArrayRef<Register>> VRegs) const { 457 ArgInfo OrigArg{VRegs[i], Arg.getType()}; 276 lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef<Register> VRegs, Register SwiftErrorVReg) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | CallLowering.h | 269 /// by \p Val, into the specified virtual registers \p VRegs. 277 ArrayRef<Register> VRegs, 281 return lowerReturn(MIRBuilder, Val, VRegs); 289 ArrayRef<Register> VRegs) const { 296 /// arguments, described by \p VRegs, for GlobalISel. Each argument 297 /// must end up in the related virtual registers described by \p VRegs. 298 /// In other words, the first argument should end up in \c VRegs[0], 299 /// the second in \c VRegs[1], and so on. For each argument, there will be one 307 ArrayRef<ArrayRef<Register>> VRegs) const { 276 lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef<Register> VRegs, Register SwiftErrorVReg) const argument
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H A D | LegalizerHelper.h | 173 SmallVectorImpl<Register> &VRegs); 178 SmallVectorImpl<Register> &VRegs, 199 /// Produce a merge of values in \p VRegs to define \p DstReg. Perform a merge 203 /// \p VRegs should each have type \p GCDTy. This type should be greatest 211 /// \p VRegs will be cleared, and the the result \p NarrowTy register pieces 212 /// will replace it. Returns The complete LCMTy that \p VRegs will cover when 215 SmallVectorImpl<Register> &VRegs,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | IRTranslator.cpp | 183 auto *VRegs = VMap.getVRegs(Val); 195 VRegs->push_back(MRI->createGenericVirtualRegister(Ty)); 196 return *VRegs; 205 llvm::copy(EltRegs, std::back_inserter(*VRegs)); 209 VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0])); 210 bool Success = translate(cast<Constant>(Val), VRegs->front()); 217 return *VRegs; 221 return *VRegs; 358 ArrayRef<Register> VRegs; local 360 VRegs 1339 SmallVector<llvm::SrcOp, 4> VRegs; local [all...] |
H A D | LegalizerHelper.cpp | 144 SmallVectorImpl<Register> &VRegs) { 146 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 147 MIRBuilder.buildUnmerge(VRegs, Reg); 152 SmallVectorImpl<Register> &VRegs, 164 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 165 MIRBuilder.buildUnmerge(VRegs, Reg); 181 VRegs.push_back(NewReg); 270 SmallVectorImpl<Register> &VRegs, 276 int NumOrigSrc = VRegs.size(); 293 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs 143 extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl<Register> &VRegs) argument 150 extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy, SmallVectorImpl<Register> &VRegs, SmallVectorImpl<Register> &LeftoverRegs) argument 269 buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, SmallVectorImpl<Register> &VRegs, unsigned PadStrategy) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 168 SmallVectorImpl<unsigned> &VRegs) const;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.h | 161 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 122 return decodeRegisterClass(Inst, RegNo, VRegs);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 2062 SmallVector<CalleeSavedInfo, 18> VRegs; local 2104 VRegs.push_back(CSI[i]); 2248 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 2249 int FI = VRegs[i].getFrameIdx();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 477 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 1209 RegNo = VRegs[IntVal];
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